fm93cs56 Fairchild Semiconductor, fm93cs56 Datasheet

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fm93cs56

Manufacturer Part Number
fm93cs56
Description
Microwire ? Bus Interface 2048-bit Serial Eeprom With Data Protect And Sequential Read
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor International
FM93CS56 Rev. C.1
FM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized
as 128 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
FM93CS56 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the FM93CS56, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
tor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
“LZ” and “L” versions of FM93CS56 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
DO
CS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
DECODER
REGISTER
REGISTER
PROTECT
DATA IN/OUT REGISTER
DATA OUT BUFFER
READ/WRITE AMPS
EEPROM ARRAY
16
16
16 BITS
CONTROL LOGIC
GENERATORS
WRITE ENABLE
INSTRUCTION
COMPARATOR
AND CLOCK
DECODER
AND
I Wide V
I Programmable write protection
I Sequential register read
I Typical active current of 200µA
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
CC
2.7V - 5.5V
HIGH VOLTAGE
GENERATOR
PROGRAM
TIMER
AND
V
PRE
PE
V
CC
SS
www.fairchildsemi.com
July 2000

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fm93cs56 Summary of contents

Page 1

... CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of FM93CS56 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations. ...

Page 2

... FM93CS56 Rev. C PRE GND CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground PE Program Enable PRE Protect Register Enable V Power Supply CC E XXX Letter Description N 8-pin DIP M8 8-pin SO ...

Page 3

... PREH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP FM93CS56 Rev. C.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93CS56 +6.5V to -0.3V FM93CS56E FM93CS56V +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...

Page 4

... KHz (Note 5) C Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) FM93CS56 Rev. C.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93CS56L/LZ +6.5V to -0.3V FM93CS56LE/LZE FM93CS56LV/LZV +300°C Power Supply ( 2000V V = 2.7V to 4.5V unless otherwise specified. Refer ...

Page 5

... This is a 8-bit field and should immediately follow the Opcode bits. In FM93CS56, only the LSB 7 bits are used for address decoding during READ, WRITE and PRWRITE instructions. During these three instructions (READ, WRITE and PRWRITE), the MSB is “ ...

Page 6

... Write Disable (WDS) instruction is executed completely removed from CC FM93CS56 Rev. C.1 the part. Input information (Start bit, Opcode and Address) for this WEN instruction should be issued as listed under Table1. The device becomes write-enabled at the end of this cycle when the CS signal is brought low ...

Page 7

... PRREAD cycle. The PRE pin should be held high during this cycle. Refer Protect Register Read cycle diagram. Though the content of this register is 8-bit wide, only the last 7 bits (LSB) are valid for FM93CS56 device. This instruction is required to enable PRCLEAR, PRWRITE and PRDS instructions and should be executed prior to executing PRCLEAR, PRWRITE and PRDS instructions ...

Page 8

... WRITE instruction description. While the device is busy recommended that no new instruction be issued. The Protect Register is permanently write-protected at the end of this cycle. Refer Protect Register Disable cycle diagram. FM93CS56 Rev. C.1 When programming is in progress, the Data-Out pin will display the programming status as either BUSY (low) or READY (high) time ...

Page 9

... > > > FM93CS56 Rev. C SKH ...

Page 10

... > > > > FM93CS56 Rev. C ...

Page 11

... Address bits patter n -> x-x-x-x-x-x-x-x; (x -> Don't Care, can PROTECT REGISTER ENABLE CYCLE (PREN) PRE Star t Bit DO 93CS56: Address bits patter n -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can FM93CS56 Rev. C D15 D14 Opcode Address Bits(2) Bits(8) High - Z -> ...

Page 12

... Star t Bit DO 93CS56: Address bits pattern -> x-A6-A5-A4-A3-A2-A1-A0; (x -> Don't Care, can 1); ( A6-A0 -> User defined ) PROTECT REGISTER DISABLE CYCLE (PRDS) PRE Star t Bit DO 93CS56: Address bits patter n -> 0-0-0-0-0-0-0-0 FM93CS56 Rev. C Opcode Address Bits(2) Bits(8) High - ...

Page 13

... FM93CS56 Rev. C ...

Page 14

... All lead tips Typ. All Leads FM93CS56 Rev. C.1 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ ...

Page 15

... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 FM93CS56 Rev. C.1 5 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ Land pattern recommendation 4 See detail A 0.002 - 0.006 (0.05 - 0.15) 0.0075 - 0.0118 (0.19 - 0.30) 0¡-8¡ DETAIL A Typ. Scale: 40X ...

Page 16

... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. FM93CS56 Rev. C.1 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...

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