GS8642Z36GB-167 GSI Technology, GS8642Z36GB-167 Datasheet

GS8642Z36GB-167

Manufacturer Part Number

GS8642Z36GB-167

Description

BGA 119/SYNCHRONOUS SRAM's 2M x 36 (72 Meg) NBT

Manufacturer

GSI Technology

Datasheet

1.GS8642Z18B-167I.pdf (34 pages)

Specifications of GS8642Z36GB-167

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 34
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119- & 209-Bump BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119- or 209-bump BGA package

• RoHS-compliant 119- and 209-bump BGA packages

Functional Description

The GS8642Z18/36/72 is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.03 4/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

available

Flow Through

Pipeline

3-1-1-1

2-1-1-1

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

(x18/x36)

tCycle

(x72)

Parameter Synopsis

1/34

-300

400

480

590

285

330

425

2.3

3.0

3.3

5.5

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8642Z18/36/72 may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS8642Z18/36/72 is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 119-bump, 165-bump or 209-bump BGA package.

GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)

-250

340

410

520

245

280

370

2.5

3.0

4.0

6.5

-200

290

350

435

220

250

315

3.0

5.0

7.5

-167

260

305

380

210

240

300

3.4

6.0

8.0

Unit

300 MHz–167 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

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