gtlp16612 Fairchild Semiconductor, gtlp16612 Datasheet

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gtlp16612

Manufacturer Part Number
gtlp16612
Description
Cmos 18-bit Ttl/gtlp Universal Bus Transceiver
Manufacturer
Fairchild Semiconductor
Datasheet

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© 1998 Fairchild Semiconductor Corporation
GTLP16612MEA
GTLP16612MTD
GTLP16612
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver
which provides TTL to GTLP signal level translation. The
device is designed to provide a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing ( 1V), reduced input threshold levels and output
edge rate control which minimizes signal settling times.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different driver
output levels and receiver threshold. GTLP output low volt-
age is typically less than 0.5V, the output high is 1.5V and
the receiver threshold is 1.0V.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
MS56A
MTD56
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS012390.prf
Features
Bidirectional interface between GTLP and TTL logic
levels
Designed with Edge Rate Control Circuit to reduce
output noise
V
receiver threshold
Submicron Core CMOS technology for low power
dissipation
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply
voltage and temperature
5V tolerant inputs and outputs on A-Port
Bus-Hold data inputs on A-Port to eliminate the need for
external pull-up resistors for unused inputs
Power up/down high impedance
TTL compatible Driver and Control inputs
A-Port outputs source/sink
Flow-through architecture optimizes PCB layout
Open drain on GTLP to support wired-or connection
REF
Package Description
pin provides external supply reference voltage for
March 1995
Revised October 1998
32 mA/ 32 mA
www.fairchildsemi.com

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gtlp16612 Summary of contents

Page 1

... GTLP16612 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver General Description The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a back- plane operating at GTLP logic levels. High speed back- plane operation is a direct result of GTLP’ ...

Page 2

... A-to-B Open Drain Outputs Functional Description The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched and clock mode. ...

Page 3

Logic Diagram 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Supply Voltage ( CCQ DC Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 5) 0. Output Sink Current into A-Port I OL ...

Page 5

DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, V Symbol V B-Port IH Others V B-Port IL Others V REF V V 3.15V 4.75V CCQ V A-Port Min to Max (Note 8) OH ...

Page 6

AC Operating Requirements Over recommended ranges of supply voltage and operating free-air temperature, V Symbol f Max Clock Frequency CLOCK t Pulse Duration W t Setup Time S t Hold Time H AC Electrical Characteristics Over recommended range of supply ...

Page 7

Test Circuits and Timing Waveforms Test Circuit for A Outputs C includes probes and jig capacitance. L Voltage Waveforms Pulse Duration (Vm 1.5V for A-Port and 1.0V for B-Port) Voltage Waveforms Setup and Hold Times (Vm 1.5V for A-Port and ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package, JEDEC MO-118 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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