HD64F3664H Renesas Electronics America, HD64F3664H Datasheet
HD64F3664H
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HD64F3664H Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3664 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked ...
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Rev. 6.00 Mar. 24, 2006 Page ii of xxviii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/3664 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...
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When the used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, ...
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Rev. 6.00 Mar. 24, 2006 Page viii of xxviii ...
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Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 Internal Block Diagram......................................................................................................... 3 1.3 Pin Arrangement ................................................................................................................... 5 1.4 Pin Functions ........................................................................................................................ 9 Section 2 CPU......................................................................................................13 2.1 Address Space and Memory Map ....................................................................................... 14 2.2 Register Configuration........................................................................................................ 17 2.2.1 General Registers................................................................................................ 18 ...
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Interrupt Flag Register 1 (IRR1)......................................................................... 56 3.2.5 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57 3.3 Reset Exception Handling .................................................................................................. 59 3.4 Interrupt Exception Handling ............................................................................................. 59 3.4.1 External Interrupts .............................................................................................. 59 3.4.2 Internal Interrupts ............................................................................................... 61 Interrupt Handling Sequence ...
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System Control Register 2 (SYSCR2) ................................................................ 86 6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................ 87 6.2 Mode Transitions and States of LSI.................................................................................... 88 6.2.1 Sleep Mode ......................................................................................................... 91 6.2.2 Standby Mode ..................................................................................................... 91 6.2.3 Subsleep Mode.................................................................................................... 92 6.2.4 ...
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Port Mode Register 1 (PMR1) .......................................................................... 116 9.1.2 Port Control Register 1 (PCR1) ........................................................................ 117 9.1.3 Port Data Register 1 (PDR1) ............................................................................ 118 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 118 9.1.5 Pin Functions .................................................................................................... 119 9.2 Port 2................................................................................................................................. ...
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Input/Output Pins.............................................................................................................. 147 11.3 Register Descriptions........................................................................................................ 147 11.3.1 Timer Counter V (TCNTV) .............................................................................. 147 11.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 148 11.3.3 Timer Control Register V0 (TCRV0) ............................................................... 148 11.3.4 Timer Control/Status Register V (TCSRV) ...
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Section 13 Watchdog Timer.............................................................................. 191 13.1 Features............................................................................................................................. 191 13.2 Register Descriptions........................................................................................................ 191 13.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 192 13.2.2 Timer Counter WD (TCWD)............................................................................ 193 13.2.3 Timer Mode Register WD (TMWD) ................................................................ 194 13.3 Operation .......................................................................................................................... 195 Section 14 ...
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Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................... 231 2 Section Bus Interface (IIC) .....................................................................233 15.1 Features............................................................................................................................. 233 15.2 Input/Output Pins.............................................................................................................. 235 15.3 Register Descriptions........................................................................................................ 236 2 15.3 Bus Data Register ...
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Permissible Signal Source Impedance .............................................................. 286 16.6.2 Influences on Absolute Accuracy ..................................................................... 286 Section 17 EEPROM......................................................................................... 287 17.1 Features............................................................................................................................. 287 17.2 Input/Output Pins.............................................................................................................. 289 17.3 Register Description ......................................................................................................... 289 17.3.1 EEPROM Key Register (EKR)......................................................................... 289 17.4 Operation .......................................................................................................................... 290 ...
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Memory Characteristics .................................................................................... 326 20.2.7 EEPROM Characteristics.................................................................................. 328 20.3 Electrical Characteristics (Mask ROM Version) .............................................................. 329 20.3.1 Power Supply Voltage and Operating Ranges .................................................. 329 20.3.2 DC Characteristics ............................................................................................ 331 20.3.3 AC Characteristics ............................................................................................ 337 20.3.4 A/D Converter Characteristics ...
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Rev. 6.00 Mar. 24, 2006 Page xviii of xxviii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTAT Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTAT Figure 1.3 Pin Arrangement of H8/3664 of F-ZTAT (FP-64E, FP-64A)......................................................................................................... 5 Figure 1.4 Pin Arrangement of H8/3664 of F-ZTAT ...
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Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 71 Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 72 Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 73 Figure 4.4 Operation when Another Interrupt is Accepted at ...
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Figure 11.2 Increment Timing with Internal Clock .................................................................... 153 Figure 11.3 Increment Timing with External Clock ................................................................... 153 Figure 11.4 OVF Set Timing ...................................................................................................... 153 Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 154 Figure 11.6 TMOV Output Timing ............................................................................................ ...
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Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the Same Timing .................................................................................... 189 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 191 Figure 13.2 Watchdog Timer Operation Example...................................................................... 195 Section 14 ...
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Figure 15.6 Master Receive Mode Operation Timing Example (1) (MLS = ACKB = 0, WAIT = 1) ............................................................................. 254 Figure 15.6 Master Receive Mode Operation Timing Example (2) (MLS = ACKB = 0, WAIT = 1) ............................................................................. 255 Figure 15.7 ...
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Section 20 Electrical Characteristics Figure 20.1 System Clock Input Timing .................................................................................... 343 Figure 20.2 RES Low Width Timing.......................................................................................... 343 Figure 20.3 Input Timing............................................................................................................ 343 2 Figure 20 Bus Interface Input/Output Timing ................................................................... 344 Figure 20.5 SCK3 Input Clock ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 24 Table 2.2 Data Transfer Instructions....................................................................................... 25 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 26 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 27 ...
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Table 7.4 Reprogram Data Computation Table .................................................................... 106 Table 7.5 Additional-Program Data Computation Table ...................................................... 106 Table 7.6 Programming Time ............................................................................................... 106 Table 7.7 Flash Memory Operating States............................................................................ 111 Section 10 Timer A Table 10.1 Pin Configuration.................................................................................................. 140 Section 11 ...
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Section 20 Electrical Characteristics Table 20.1 Absolute Maximum Ratings ................................................................................. 311 Table 20.2 DC Characteristics (1)........................................................................................... 314 Table 20.2 DC Characteristics (2)........................................................................................... 318 Table 20.2 DC Characteristics (3)........................................................................................... 319 Table 20.3 AC Characteristics ................................................................................................ 320 2 Table 20 ...
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Rev. 6.00 Mar. 24, 2006 Page xxviii of xxviii ...
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Features • High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions • Various peripheral functions Timer A (can be ...
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Section 1 Overview • Supports various power-down modes TM Note: F-ZTAT is a trademark of Renesas Technology Corp. • Compact package Package Code LQFP-64 FP-64E QFP-64 FP-64A LQFP-48 FP-48F LQFP-48 FP-48B SDIP-42 DP-42S Only LQFP-64 (FP-64E) for H8/3664N package Rev. ...
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Internal Block Diagram System Subclock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTAT CPU clock H8/300H Data bus (lower) RAM ROM Timer W SCI3 Watchdog Timer ...
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Section 1 Overview System Subclock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD SDA SCL Note : The H8/3664N is a stacked-structure product in which an EEPROM chip is mounted on the H8/3664F-ZTAT TM Figure 1.2 ...
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Pin Arrangement P14/IRQ0 52 P15/IRQ1 53 P16/IRQ2 P17/IRQ3/TRGV 54 55 PB4/AN4 56 PB5/AN5 57 PB6/AN6 58 PB7/AN7 59 PB3/AN3 60 PB2/AN2 PB1/AN1 61 62 PB0/AN0 Note: Do not connect NC ...
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Section 1 Overview P14/IRQ0 37 P15/IRQ1 38 P16/IRQ2 39 P17/IRQ3/TRGV 40 PB4/AN4 41 PB5/AN5 42 PB6/AN6 43 PB7/AN7 44 PB3/AN3 45 PB2/AN2 46 PB1/AN1 47 PB0/AN0 48 Figure 1.4 Pin Arrangement of H8/3664 of F-ZTAT Rev. 6.00 Mar. 24, 2006 ...
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PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 RES TEST V SS OSC2 OSC1 V CC P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P10/TMOW Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins. Figure 1.5 Pin ...
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Section 1 Overview P14/IRQ0 52 P15/IRQ1 53 P16/IRQ2 54 P17/IRQ3/TRGV PB4/AN4 55 56 PB5/AN5 57 PB6/AN6 58 PB7/AN7 59 ...
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Pin Functions Table 1.1 Pin Functions FP-64E, Type Symbol FP-64A Power source pins Clock pins OSC1 11 OSC2 System control RES 7 ...
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Section 1 Overview FP-64E, Type Symbol FP-64A NMI Interrupt pins 35 IRQ0 IRQ3 WKP0 to 13, 14, WKP5 Timer A TMOW 23 Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer ...
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FP-64E, Type Symbol FP-64A I/O ports PB7 to PB0 P17 to P14 P12 to P10 P22 to P20 P57 to P50 13,14, (P55 to P50 ...
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Section 1 Overview Rev. 6.00 Mar. 24, 2006 Page 12 of 412 REJ09B0142-0600 ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs ...
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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. HD64F3664 (Flash memory version) H'0000 Interrupt vector ...
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HD6433662 (Mask ROM version) H'0000 H'0000 Interrupt vector H'0033 H'0033 H'0034 H'0034 On-chip ROM (16 kbytes) H'3FFF H'5FFF Not used H'FB80 H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF7F H'FF80 H'FF80 Internal I/O register H'FFFF H'FFFF Figure 2.1 Memory Map (2) ...
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Section 2 CPU Rev. 6.00 Mar. 24, 2006 Page 16 of 412 REJ09B0142-0600 HD64N3664 (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) ...
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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register ...
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), ...
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Section 2 CPU Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev. ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: ...
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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...
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Table 2.2 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd, ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and ...
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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ...
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ...
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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result ...
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Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC ...
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR LDC B/W Moves the ...
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Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — else next ≠ 0 then EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
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Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU ...
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Section 2 CPU (1) Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and ...
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Absolute Address—@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper ...
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Section 2 CPU (8) Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is ...
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Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective ...
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Section 2 CPU Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Rev. 6.00 ...
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Basic Bus Cycle CPU operation is synchronized by a system clock (φ subclock (φ edge of φ or φ to the next rising edge is called one state. A bus cycle consists of two states or SUB ...
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Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and ...
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CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. In the program halt state there are a sleep mode, ...
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Section 2 CPU Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers ...
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Bit Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special ...
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Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and ...
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As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the ...
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Section 2 CPU (2) Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level ...
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As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change that P57 and P56 change from input pins to output pins. To ...
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Section 2 CPU Rev. 6.00 Mar. 24, 2006 Page 50 of 412 REJ09B0142-0600 ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES ...
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Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address Relative Module Exception Sources RES pin Reset Watchdog timer Reserved for system use External interrupt NMI pin CPU Trap instruction (#0) Address break Break conditions satisfied CPU Direct ...
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Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt flag register 1 (IRR1) • Wakeup interrupt flag ...
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Bit Name Value 6 ...
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Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Initial Bit Bit Name Value 7 IENDT 0 6 IENTA 0 5 IENWP 0 IEN3 0 2 ...
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Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Initial Bit Bit Name Value 7 IRRDT 0 6 IRRTA ...
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Initial Bit Bit Name Value 0 IRRl0 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Initial Bit Bit Name Value IWPF5 0 ...
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Section 3 Exception Handling Initial Bit Bit Name Value 2 IWPF2 0 1 IWPF1 0 0 IWPF0 0 Rev. 6.00 Mar. 24, 2006 Page 58 of 412 REJ09B0142-0600 R/W Description R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin ...
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Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure ...
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Section 3 Exception Handling (3) WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing ...
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Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests generated by execution of ...
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Section 3 Exception Handling SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC ...
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Figure 3.3 Interrupt Sequence Section 3 Exception Handling Rev. 6.00 Mar. 24, 2006 Page 63 of 412 REJ09B0142-0600 ...
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Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program ...
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CCR I bit Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 CCR I bit Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Interrupts masked. (Another possibility is to disable the ...
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Section 3 Exception Handling Rev. 6.00 Mar. 24, 2006 Page 66 of 412 REJ09B0142-0600 ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
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Section 4 Address Break 4.1 Register Descriptions Address break has the following registers. • Address break control register (ABRKCR) • Address break status register (ABRKSR) • Break address register (BARH, BARL) • Break data register (BDRH, BDRL) 4.1.1 Address Break ...
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Initial Bit Bit Name Value 1 DCMP1 0 0 DCMP0 0 [Legend] X: Don't care. When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of ...
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Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Initial Bit Bit Name Value 7 ABIF 0 6 ABIE — ...
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Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set the combination of the address ...
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch Address 025C bus Interrupt request Figure 4.2 Address Break Interrupt ...
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Usage Notes When an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch instruction is not satisfied is executed (see figure 4.3), note that an address ...
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Section 4 Address Break When another interrupt request is accepted before an instruction to which an address break is set is executed, exception handling of an address break interrupt is not executed. However, the ABIF bit is set to 1 ...
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When an address break is set to an instruction as a branch destination of a conditional branch instruction, the instruction set when the condition of the branch instruction is not satisfied is not executed, and an address break is generated. ...
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Section 4 Address Break Rev. 6.00 Mar. 24, 2006 Page 76 of 412 REJ09B0142-0600 ...
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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty ...
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Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Figure 5.2 shows a block diagram of ...
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Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 500 Ω R (max (max 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. OSC 1 OSC 2 Figure 5.5 Typical ...
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Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by ...
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Pin Connection when Not Using Subclock When the subclock is not used, connect pin X figure 5.10. Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler 13-bit counter using the system ...
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Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will ...
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Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
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Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • System control register 1 (SYSCR1) • System control register 2 (SYSCR2) • Module standby control register 1 (MSTCR1) 6.1.1 System Control Register 1 ...
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Initial Bit Bit Name Value 3 NESEL 0 Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 ...
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value 7 SMSEL 0 6 LSON 0 5 DTON 0 4 MA2 0 3 MA1 0 2 ...
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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value MSTIIC 0 5 MSTS3 0 4 MSTAD 0 3 MSTWD ...
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing ...
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL [Legend] X: Don't care. Note: * When a state transition is performed while SMSEL is ...
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Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Function Active Mode System clock oscillator Functioning Subclock oscillator Functioning CPU Instructions Functioning operations Registers Functioning RAM Functioning IO ports Functioning External IRQ3 to IRQ0 Functioning interrupts WKP5 ...
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Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, ...
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Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than timer A is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, ...
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Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition ...
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Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition ...
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The features of the 32-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is ...
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Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 ...
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Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory power control register (FLPWCR) • Flash memory ...
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Section 7 ROM Bit Initial Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 ...
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Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
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Section 7 ROM 7.2.5 Flash Memory Enable Register (FENR) Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR. Bit Initial Bit Name Value 7 FLSHE 0 6 ...
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Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare ...
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Section 7 ROM Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) ...
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 MHz 9,600 bps MHz 4,800 bps MHz ...
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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the ...
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The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait ...
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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table ...
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Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification ...
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Section 7 ROM Increment address Note: *The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev. 6.00 Mar. 24, 2006 Page 108 ...
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Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because ...
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Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re- entered by re-setting the P ...
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Table 7.7 Flash Memory Operating States LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Flash Memory Operating State PDWND = 0 (Initial value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode ...
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Section 7 ROM Rev. 6.00 Mar. 24, 2006 Page 112 of 412 REJ09B0142-0600 ...
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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/3664N TM ...
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Section 8 RAM Rev. 6.00 Mar. 24, 2006 Page 114 of 412 REJ09B0142-0600 ...
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The group of this LSI has twenty-nine general I/O ports (twenty-seven ports for H8/3664N) and eight general input-only ports. Port large current port, which can drive 20 mA (@V V) when a low level signal is output. ...
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 ...
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Initial Bit Bit Name Value 0 TMOW 0 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 0 ...
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Section 9 I/O Ports 9.1.3 Port Data Register 1 (PDR1) PDR1 is a general I/O port data register of port 1. Initial Bit Bit Name Value 7 P17 0 6 P16 0 5 P15 0 4 P14 0 3 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. • P17/IRQ3/TRGV Pin Register PMR1 PCR1 Bit Name IRQ3 PCR17 Setting value [Legend] X: Don't care. • P16/IRQ2 Pin ...
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Section 9 I/O Ports • P14/IRQ0 Pin Register PMR1 Bit Name IRQ0 Setting value 0 1 [Legend] X: Don't care. • P12 Pin Register PCR1 Bit Name PCR12 Setting value 0 1 • P11 Pin Register PCR1 Bit Name PCR11 ...
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Port 2 Port general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of ...
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Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Initial Bit Bit Name Value 3 ...
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P21/RXD Pin Register SCR3 PCR2 Bit Name RE PCR21 Setting Value [Legend] X: Don't care. • P20/SCK3 Pin Register SCR3 Bit Name CKE1 Setting Value [Legend] X: Don't care. Pin ...
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Section 9 I/O Ports 9.3 Port 5 Port general I/O port also functioning pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting 2 of ...
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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 1 WKP1 ...
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Section 9 I/O Ports Initial Bit Bit Name Value 0 WKP0 0 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Initial Bit Bit Name ...
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Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Initial Bit Bit Name Value 7 P57 0 6 P56 0 5 P55 0 4 P54 0 3 P53 0 2 P52 0 ...
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Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL Pin Register ICCR PCR5 Bit Name ICE PCR57 Setting Value [Legend] X: Don't ...
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P54/WKP4 Pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Setting Value [Legend] X: Don't care. • P53/WKP3 Pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Setting Value [Legend] X: ...
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Section 9 I/O Ports • P51/WKP1 Pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Setting Value [Legend] X: Don't care. • P50/WKP0 Pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Setting Value ...
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Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of ...
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Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P76/TMOV Pin Register TCSRV Bit Name OS3 to OS0 Setting Value 0000 Other than the above values [Legend] X: ...
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Port 8 Port general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions ...
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Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Initial Bit Bit Name Value 7 PCR87 0 6 PCR86 0 5 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. • P87 Pin Register PCR8 Bit Name PCR87 Pin Function Setting Value 0 P87 input pin 1 P87 output pin • P86 Pin Register ...
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Section 9 I/O Ports • P84/FTIOD Pin Register TMRW Bit Name PWMD IOD2 Setting Value [Legend] X: Don't care. • P83/FTIOC Pin Register TMRW Bit Name PWMC IOC2 Setting Value ...
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P82/FTIOB Pin Register TMRW Bit Name PWMB IOB2 Setting Value [Legend] X: Don't care. • P81/FTIOA Pin Register TIOR0 Bit Name IOA2 IOA1 Setting Value ...
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Section 9 I/O Ports 9.6 Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. Port B has the following register. • ...
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Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features • Timer ...
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Section 10 Timer A 1 / TMOW / [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt ...
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Register Descriptions Timer A has the following registers. • Timer mode register A (TMA) • Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Bit ...
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Section 10 Timer A Bit Initial Bit Name Value 2 TMA2 0 1 TMA1 0 0 TMA0 0 [Legend] X: Don't care. 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-counter, which is incremented by internal clock input. ...
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Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared up-counting of ...
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Section 10 Timer A 10.5 Usage Note When the clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock ...
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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...
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Section 11 Timer V TRGV Clock select TMCIV PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register ...
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Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 11.3 Register Descriptions Time V has the following registers. • Timer ...
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Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV ...
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Initial Bit Bit Name Value 4 CCLR1 0 3 CCLR0 0 2 CKS2 0 1 CKS1 0 0 CKS0 0 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 ...
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Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Bit Name Value 7 CMFB 0 6 CMFA 0 5 OVF 0 ...
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Initial Bit Bit Name Value 1 OS1 0 0 OS0 0 OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled ...
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Section 11 Timer V Initial Bit Bit Name Value ICKS0 0 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer ...
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Internal clock TCNTV input clock N – 1 TCNTV Figure 11.2 Increment Timing with Internal Clock TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 11.3 Increment Timing with External Clock TCNTV H'FF Overflow signal OVF ...
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Section 11 Timer V TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing Compare match A signal Timer V output pin Compare match A signal TCNTV Figure 11.7 Clear Timing by Compare ...
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TMRIV(External counter reset input pin ) TCNTV reset signal TCNTV Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an ...
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Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as ...
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Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal is generated in the ...
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Section 11 Timer V Address Internal write signal TCNTV TCORA Compare match signal Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer W. Table 12.1 Timer W Functions Item Counter Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI ...
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Internal clock: /2 Clock /4 selector /8 External clock: FTCI Comparator [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 ...
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Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation External clock input FTCI Input capture/output FTIOA compare A Input capture/output FTIOB compare B Input capture/output FTIOC compare C Input ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Bit Name Value 7 CTS 0 BUFEB 0 4 BUFEA 0 PWMD 0 ...
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Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Bit Name Value 7 CCLR 0 6 CKS2 0 5 CKS1 ...
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Initial Bit Bit Name Value 0 TOA 0 [Legend] X: Don't care. Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. ...
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Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Bit Name Value 7 OVF 0 IMFD 0 2 IMFC 0 ...
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Initial Bit Bit Name Value 1 IMFB 0 0 IMFA 0 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Initial Bit Bit Name ...
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Section 12 Timer W Initial Bit Bit Name Value 5 IOB1 0 4 IOB0 0 IOA2 0 1 IOA1 0 0 IOA0 0 [Legend] X: Don't care. Rev. 6.00 Mar. 24, 2006 Page 168 of 412 ...
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Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Initial Bit Bit Name Value IOD2 0 5 IOD1 0 4 ...
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Section 12 Timer W Initial Bit Bit Name Value 1 IOC1 0 0 IOC0 0 [Legend] X: Don't care. 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in ...