HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet
HD64F3694FY
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HD64F3694FY Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/3694 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked ...
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Rev.5.00 Nov. 02, 2005 Page ii of xxviii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/3694 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible ...
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When the used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, ...
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Rev.5.00 Nov. 02, 2005 Page viii of xxviii ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Internal Block Diagram.......................................................................................................... 4 1.3 Pin Arrangement .................................................................................................................... 6 1.4 Pin Functions ......................................................................................................................... 9 Section 2 CPU......................................................................................................13 2.1 Address Space and Memory Map ........................................................................................ 14 2.2 Register Configuration......................................................................................................... 17 2.2.1 General Registers.................................................................................................... 18 ...
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Wakeup Interrupt Flag Register (IWPR) ................................................................ 55 3.3 Reset Exception Handling.................................................................................................... 56 3.4 Interrupt Exception Handling .............................................................................................. 57 3.4.1 External Interrupts .................................................................................................. 57 3.4.2 Internal Interrupts ................................................................................................... 58 3.4.3 Interrupt Handling Sequence .................................................................................. 58 3.4.4 Interrupt Response Time......................................................................................... 60 ...
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Mode Transitions and States of LSI..................................................................................... 80 6.2.1 Sleep Mode ............................................................................................................. 83 6.2.2 Standby Mode ......................................................................................................... 83 6.2.3 Subsleep Mode........................................................................................................ 83 6.2.4 Subactive Mode ...................................................................................................... 84 6.3 Operating Frequency in Active Mode.................................................................................. 84 6.4 Direct Transition .................................................................................................................. 85 6.4.1 ...
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Port Pull-Up Control Register 1 (PUCR1)............................................................ 112 9.1.5 Pin Functions ........................................................................................................ 112 9.2 Port 2.................................................................................................................................. 114 9.2.1 Port Control Register 2 (PCR2) ............................................................................ 115 9.2.2 Port Data Register 2 (PDR2) ................................................................................ 115 9.2.3 Pin Functions ........................................................................................................ 116 9.3 Port ...
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Time Constant Registers A and B (TCORA, TCORB) ........................................ 139 11.3.3 Timer Control Register V0 (TCRV0) ................................................................... 140 11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 142 11.3.5 Timer Control Register V1 (TCRV1) ................................................................... 143 11.4 Operation ........................................................................................................................... 144 11.4.1 ...
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Timer Control/Status Register WD (TCSRWD) .................................................. 184 13.2.2 Timer Counter WD (TCWD)................................................................................ 185 13.2.3 Timer Mode Register WD (TMWD) .................................................................... 186 13.3 Operation ........................................................................................................................... 187 Section 14 Serial Communication Interface 3 (SCI3)....................................... 189 14.1 Features.............................................................................................................................. 189 14.2 Input/Output Pins............................................................................................................... ...
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Section Bus Interface 2 (IIC2) ................................................................231 15.1 Features.............................................................................................................................. 231 15.2 Input/Output Pins ............................................................................................................... 233 15.3 Register Descriptions ......................................................................................................... 233 2 15.3 Bus Control Register 1 (ICCR1)..................................................................... 234 2 15.3 Bus Control Register ...
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A/D Conversion Accuracy Definitions .............................................................................. 274 16.6 Usage Notes ....................................................................................................................... 276 16.6.1 Permissible Signal Source Impedance .................................................................. 276 16.6.2 Influences on Absolute Accuracy ......................................................................... 276 Section 17 EEPROM......................................................................................... 277 17.1 Features.............................................................................................................................. 277 17.2 Input/Output Pins............................................................................................................... 279 17.3 Register Description ...
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Register Bits....................................................................................................................... 307 20.3 Registers States in Each Operating Mode .......................................................................... 311 Section 21 Electrical Characteristics .................................................................315 21.1 Absolute Maximum Ratings .............................................................................................. 315 21.2 Electrical Characteristics (F-ZTAT™ Version, EEPROM Stacked F-ZTAT 21.2.1 Power Supply Voltage and Operating Ranges ...................................................... ...
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Appendix D Package Dimensions ..................................................................... 405 Appendix E EEPROM Stacked-Structure Cross-Sectional View ..................... 410 Main Revisions and Additions in this Edition..................................................... 411 Index .................................................................................................................. 415 Rev.5.00 Nov. 02, 2005 Page xviii of xxviii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTAT Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) ............................ 5 Figure 1.3 Pin Arrangement of H8/3694 Group of F-ZTAT (FP-64E, FP-64A).......................................................................................................... 6 Figure 1.4 Pin ...
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Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70 Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70 Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70 ...
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Figure 11.9 Pulse Output Example ............................................................................................. 148 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 149 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 150 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 151 Figure ...
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Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3........................................................................................... 190 Figure 14.2 Data Format in Asynchronous Communication ...................................................... 205 Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, ...
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Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 254 Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 254 Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 255 Figure 15.14 Transmit Mode Operation Timing......................................................................... 256 Figure 15.15 Receive Mode Operation Timing .......................................................................... ...
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Figure 21.3 Input Timing............................................................................................................ 352 2 Figure 21 Bus Interface Input/Output Timing ................................................................... 352 Figure 21.5 SCK3 Input Clock Timing ...................................................................................... 353 Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 353 Figure 21.7 EEPROM Bus Timing............................................................................................. ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 24 Table 2.2 Data Transfer Instructions....................................................................................... 25 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 26 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 27 ...
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Table 7.5 Additional-Program Data Computation Table ...................................................... 100 Table 7.6 Programming Time ............................................................................................... 100 Table 7.7 Flash Memory Operating States............................................................................ 105 Section 10 Timer A Table 10.1 Pin Configuration.................................................................................................. 132 Section 11 Timer V Table 11.1 Pin Configuration.................................................................................................. 138 Table ...
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions................................................................. 292 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 315 Table 21.2 DC Characteristics (1)........................................................................................... 318 Table 21.2 DC Characteristics (2)........................................................................................... 322 ...
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Rev.5.00 Nov. 02, 2005 Page xxviii of xxviii ...
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Features High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions Various peripheral functions Timer A (can be used as a time base for ...
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Section 1 Overview On-chip memory Product Classification Flash memory version H8/3694F HD64F3694 HD64F3694G TM (F-ZTAT version) Mask ROM version H8/3694 H8/3693 H8/3692 H8/3691 H8/3690 EEPROM Flash H8/3694N stacked memory version version (512 bytes) Mask-ROM version General I/O ports I/O pins: ...
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Compact package Package Code LQFP-64 FP-64E QFP-64 FP-64A LQFP-48 FP-48F LQFP-48 FP-48B QFN-48 TNP-48 Only LQFP-64 (FP-64E) for H8/3694N package Body Size Pin Pitch 10.0 10.0 mm 0.5 mm 14.0 14.0 mm 0.8 mm 10.0 10.0 mm 0.65 mm 7.0 ...
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Section 1 Overview 1.2 Internal Block Diagram System Subclock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTAT Rev.5.00 Nov. 02, 2005 Page 4 of 418 REJ09B0028-0500 ...
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System Subclock clock generator generator P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD SDA SCL Note: The HD64N3694G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3694G (F-ZTAT The HD6483694G is a stacked-structure ...
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Section 1 Overview 1.3 Pin Arrangement P14/IRQ0 51 52 P15/IRQ1 53 P16/IRQ2 54 P17/IRQ3/TRGV 55 PB4/AN4 56 PB5/AN5 57 PB6/AN6 ...
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P14/IRQ0 37 P15/IRQ1 38 P16/IRQ2 39 P17/IRQ3/TRGV 40 PB4/AN4 41 PB5/AN5 42 PB6/AN6 43 PB7/AN7 44 PB3/AN3 45 PB2/AN2 46 PB1/AN1 47 PB0/AN0 48 Figure 1.4 Pin Arrangement ...
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Section 1 Overview P14/IRQ0 52 P15/IRQ1 P16/IRQ2 53 54 P17/IRQ3/TRGV 55 PB4/AN4 56 PB5/AN5 57 PB6/AN6 58 PB7/AN7 59 ...
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Pin Functions Table 1.1 Pin Functions Pin No. FP-64E Type Symbol FP-64A Power source pins Clock OSC1 11 pins OSC2 RES System ...
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Section 1 Overview Pin No. FP-64E Type Symbol FP-64A Timer A TMOW 23 Timer V TMOV 30 TMCIV 29 TMRIV 28 TRGV 54 Timer W FTCI 36 FTIOA I/O FTIOD ...
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Pin No. FP-64E Type Symbol FP-64A I/O ports P76 I/O P74 P87 I/O P80 Notes: 1. These pins are only available for the I bus is ...
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Section 1 Overview Rev.5.00 Nov. 02, 2005 Page 12 of 418 REJ09B0028-0500 ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight ...
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Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. HD64F3694, HD64F3694G (Flash memory version) H'0000 Interrupt ...
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HD6433692, HD6433692G (Mask ROM version) H'0000 Interrupt vector H'0033 H'0034 On-chip ROM (16 kbytes) H'3FFF Not used H'F730 Internal I/O register H'F74F Not used H'FD80 On-chip RAM (512 bytes) H'FF7F H'FF80 Internal I/O register H'FFFF Figure 2.1 Memory Map (2) ...
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Section 2 CPU Rev.5.00 Nov. 02, 2005 Page 16 of 418 REJ09B0028-0500 HD64N3694G HD6483694G (On-chip EEPROM module) H'0000 User area (512 bytes) H'01FF Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) ...
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Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register ...
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Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between stack pointer and the stack area. SP (ER7) ...
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Section 2 CPU Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W Rev.5.00 ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: ...
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Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined ...
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Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) MOVTPE B Rs POP W/L ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register (immediate byte ...
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Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – ...
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Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a ...
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Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B ...
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Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand ...
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Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field op 2.5 Addressing Modes and Effective Address Calculation ...
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Table 2.10 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect Register Direct—Rn ...
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Section 2 CPU Register indirect with pre-decrement—@-ERn The value subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address ...
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The resulting value should be an even number. Memory Indirect—@@aa:8 This mode can ...
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Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. ...
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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation PC contents Sign extension Memory contents ...
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock ( ) or a subclock ( edge the next rising edge is called one state. A bus cycle consists of two states ...
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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing ...
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state there are ...
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Reset state Reset occurs Program halt state 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to ...
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Section 2 CPU Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure ...
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Prior to executing BSET instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 BSET instruction executed instruction BSET #0, @PDR5 After executing BSET instruction P57 P56 Input/output Input Input Pin state ...
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Section 2 CPU Prior to executing BSET instruction MOV.B #80, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 BSET instruction executed ...
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BCLR instruction is shown below assumed that a high-level signal will be input to this input pin. Prior to executing BCLR instruction P57 P56 Input/output Input Input Pin state Low High level level ...
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Section 2 CPU Prior to executing BCLR instruction MOV.B #3F, R0L MOV.B R0L, @RAM0 MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 BCLR instruction executed ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. ...
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Section 3 Exception Handling Relative Module Exception Sources CPU Direct transition by executing the SLEEP instruction External interrupt IRQ0 pin Low-voltage detection interrupt* IRQ1 IRQ2 IRQ3 WKP Timer A Overflow Reserved for system use Timer W Timer W input capture ...
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Register Descriptions Interrupts are controlled by the following registers. Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge ...
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Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Bit Name Value 7, 6 All 1 5 ...
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Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Initial Bit Bit Name Value 7 IENDT 0 6 IENTA 0 5 IENWP IEN3 0 2 IEN2 ...
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Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Initial Bit Bit Name Value 7 IRRDT 0 6 IRRTA ...
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Initial Bit Bit Name Value 0 IRRl0 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Initial Bit Bit Name Value 7, 6 All 1 5 IWPF5 0 4 IWPF4 ...
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Section 3 Exception Handling Initial Bit Bit Name Value 2 IWPF2 0 1 IWPF1 0 0 IWPF0 0 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state ...
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Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by ...
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Section 3 Exception Handling RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction 3.4.2 Internal Interrupts Each on-chip peripheral ...
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When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the ...
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Section 3 Exception Handling SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC ...
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Figure 3.3 Interrupt Sequence Section 3 Exception Handling Rev.5.00 Nov. 02, 2005 Page 61 of 418 REJ09B0028-0500 ...
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Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can ...
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Section 4 Address Break 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Initial Bit Bit Name Value 7 RTINTE 1 6 CSEL1 0 5 CSEL0 0 4 ACMP2 0 3 ACMP1 0 2 ACMP0 0 1 DCMP1 ...
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When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When ...
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Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the ...
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Figures 4.2 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting • ABRKCR = H'80 • BAR = H'025A NOP instruc- tion prefetch Address 0258 bus Interrupt ...
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Section 4 Address Break Rev.5.00 Nov. 02, 2005 Page 68 of 418 REJ09B0028-0500 ...
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Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty ...
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Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Figure 5.2 shows a block diagram of ...
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Table 5.1 Crystal Resonator Parameters Frequency (MHz (max) 500 S C (max 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 ...
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Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by ...
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Pin Connection when Not Using Subclock When the subclock is not used, connect pin X figure 5.10. Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler 13-bit counter using the system ...
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Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will ...
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Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
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Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Initial Bit Bit Name Value 7 SSBY 0 6 STS2 0 5 STS1 0 4 STS0 0 3 NESEL 0 2 ...
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Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 states 1 0 128 states 1 ...
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Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Bit Name Value 7 SMSEL 0 6 LSON 0 5 DTON 0 4 MA2 0 3 MA1 0 2 ...
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Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value MSTIIC 0 5 MSTS3 0 4 MSTAD 0 3 MSTWD 0 ...
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing ...
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL Legend Don’t care. * When a state transition is performed while SMSEL is ...
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Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Function Active Mode System clock oscillator Functioning Subclock oscillator Functioning CPU Instructions Functioning operations Registers Functioning RAM Functioning IO ports Functioning External IRQ3 to IRQ0 Functioning interrupts WKP5 ...
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Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, ...
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Section 6 Power-Down Modes cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the ...
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Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction ...
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Section 6 Power-Down Modes Example Direct transition time = ( 8tw + (8192 + 14) tosc = 24tw + 8206tosc (when the CPU operating clock of Legend tosc: OSC clock cycle time tw: watch clock cycle time tcyc: ...
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The features of the 32-kbyte flash memory built into the flash memory version are summarized below. Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as ...
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Section 7 ROM H'0000 Erase unit H'0080 1kbyte H'0380 H'0400 Erase unit H'0480 1kbyte H'0780 H'0800 Erase unit H'0880 1kbyte H'0B80 H'0C00 Erase unit H'0C80 1kbyte H'0F80 H'1000 Erase unit H'1080 28 kbytes H'7F80 Figure 7.1 Flash Memory Block Configuration ...
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Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Initial ...
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Section 7 ROM Initial Bit Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written ...
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Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
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Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power ...
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On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in ...
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Section 7 ROM pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one ...
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Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps MHz 9,600 bps MHz 4,800 ...
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Reset-start Program/erase? Yes Transfer user program/erase control program to RAM Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program ...
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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the ...
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The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait ...
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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table ...
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For a dummy write to a verify address, write 1-byte data H' address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. ...
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Section 7 ROM Increment address Note: *The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev.5.00 Nov. 02, 2005 Page 102 of ...
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Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because ...
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Section 7 ROM entered by re-setting the bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.6 Programmer Mode ...
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Table 7.7 Flash Memory Operating States LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Flash Memory Operating State PDWND = 0 (Initial value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode ...
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Section 7 ROM Rev.5.00 Nov. 02, 2005 Page 106 of 418 REJ09B0028-0500 ...
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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/3694F TM ...
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Section 8 RAM Rev.5.00 Nov. 02, 2005 Page 108 of 418 REJ09B0028-0500 ...
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The group of this LSI has twenty-nine general I/O ports (twenty-seven general I/O ports in the H8/3694N) and eight general input-only ports. Port large current port, which can drive 20 mA (@V = 1.5 V) when a ...
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 3, ...
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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 PCR14 ...
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 ...
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P15/IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value Legend: X: Don't care. P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Setting value Legend: X: Don't care. ...
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Section 9 I/O Ports P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Setting value Legend: X: Don't care. 9.2 Port 2 Port general I/O port also functioning as a SCI3 I/O ...
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Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Initial Bit Bit Name Value PCR22 0 1 PCR21 0 0 PCR20 ...
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Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Setting 0 0 Value Legend: X: Don't care. ...
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Port 5 Port general I/O port also functioning pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting 2 of the I C bus ...
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Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value 7, 6 All 0 5 WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 ...
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Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Initial Bit Bit Name Value 7 PCR57 0 6 PCR56 0 5 PCR55 0 4 PCR54 ...
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Section 9 I/O Ports 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7, 6 All 0 5 PUCR55 0 4 ...
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P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Setting 0 0 Value Legend: X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 ...
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Section 9 I/O Ports P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Setting 0 0 Value Legend: X: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Setting 0 0 Value ...
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P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Setting 0 0 Value Legend: X: Don't care. 9.4 Port 7 Port general I/O port also functioning as a timer V I/O pin. Each pin ...
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Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Initial Bit Bit Name Value 7 6 PCR76 0 5 PCR75 0 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Setting 0000 0 Value 1 Other than X the above values Legend: X: ...
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Section 9 I/O Ports 9.5 Port 8 Port general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W ...
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Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Initial Bit Bit Name Value 7 P87 0 6 P86 0 5 P85 0 4 P84 0 3 P83 0 2 P82 0 ...
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Section 9 I/O Ports P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting 0 P85 input pin Value 1 P85 output pin P84/FTIOD pin Register TIOR1 Bit Name IOD2 IOD1 Setting 0 0 Value ...
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P82/FTIOB pin Register TIOR0 Bit Name IOB2 IOB1 Setting 0 0 Value Legend: X: Don't care. P81/FTIOA pin Register TIOR0 Bit Name IOA2 IOA1 Setting 0 0 Value ...
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Section 9 I/O Ports 9.6 Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. Port B has the following register. Port ...
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Timer 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features Timer A ...
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Section 10 Timer A 1 / TMOW / [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt ...
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Register Descriptions Timer A has the following registers. Timer mode register A (TMA) Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Initial Bit Bit ...
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Section 10 Timer A Initial Bit Bit Name Value 2 TMA2 0 1 TMA1 0 0 TMA0 0 Legend: X: Don't care. 10.3.2 Timer Counter A (TCA) TCA is an 8-bit readable up-counter, which is incremented by internal clock input. ...
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Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared up-counting of ...
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Section 10 Timer A Rev.5.00 Nov. 02, 2005 Page 136 of 418 REJ09B0028-0500 ...
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Timer 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an ...
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Section 11 Timer V TRGV Clock select TMCIV PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register ...
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Register Descriptions Time V has the following registers. Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) 11.3.1 Timer ...
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Section 11 Timer V 11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Initial Bit Bit Name Value 7 CMIEB 0 6 CMIEA 0 ...
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Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 TCRV1 Bit 0 ICKS0 Description ...
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Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Bit Name Value 7 CMFB 0 6 CMFA 0 5 OVF ...
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OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the ...
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Section 11 Timer V 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, ...
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Internal clock TCNTV input clock N – 1 TCNTV Figure 11.2 Increment Timing with Internal Clock TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 11.3 Increment Timing with External Clock TCNTV H'FF Overflow signal OVF ...
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Section 11 Timer V TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing Compare match A signal Timer V output pin Compare match A signal TCNTV Figure 11.7 Clear Timing by Compare ...
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TMRIV(External counter reset input pin ) TCNTV reset signal N – 1 TCNTV Figure 11.8 Clear Timing by TMRIV Input Section 11 Timer V N H'00 Rev.5.00 Nov. 02, 2005 Page 147 of 418 REJ09B0028-0500 ...
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Section 11 Timer V 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that ...
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Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. ...
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Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal ...
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Address Internal write signal TCNTV TCORA Compare match signal Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV ...
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Section 11 Timer V Rev.5.00 Nov. 02, 2005 Page 152 of 418 REJ09B0028-0500 ...
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The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. ...
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Section 12 Timer W Table 12.1 Timer W Functions Item Counter Count clock Internal clocks: , /2, /4, /8 External clock: FTCI General registers Period (output compare/input specified in capture registers) GRA Counter clearing function GRA compare match Initial output ...
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Internal clock: /2 Clock /4 selector /8 External clock: FTCI Comparator [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 ...
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Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation External clock input FTCI Input capture/output FTIOA compare A Input capture/output FTIOB compare B Input capture/output FTIOC compare C Input ...
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Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Bit Name Value 7 CTS BUFEB 0 4 BUFEA PWMD 0 1 PWMC ...
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Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Bit Name Value 7 CCLR 0 6 CKS2 0 5 CKS1 ...
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Initial Bit Bit Name Value 0 TOA 0 Legend: X: Don't care. Note: * The change of the setting is immediately reflected in the output value. 12.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request. ...
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Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Bit Name Value 7 OVF All 1 3 IMFD 0 2 IMFC 0 Rev.5.00 Nov. 02, 2005 ...
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Initial Bit Bit Name Value 1 IMFB 0 0 IMFA 0 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Initial Bit Bit Name ...
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Section 12 Timer W Initial Bit Bit Name Value 5 IOB1 0 4 IOB0 IOA2 0 1 IOA1 0 0 IOA0 0 Legend: X: Don't care. Rev.5.00 Nov. 02, 2005 Page 162 of 418 REJ09B0028-0500 R/W ...
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Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Initial Bit Bit Name Value IOD2 0 5 IOD1 0 4 IOD0 ...
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Section 12 Timer W Initial Bit Bit Name Value 1 IOC1 0 0 IOC0 0 Legend: X: Don't care. 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in ...
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IMIEB, IMIEC, or IMIED) in TSRW is set this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA ...
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Section 12 Timer W TCNT value H'FFFF H'0000 CTS bit OVF Figure 12.2 Free-Running Counter Operation Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. ...
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TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is ...
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Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising ...
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TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 FTIOA GRA GRC Figure 12.8 Buffer Operation Example (Input Capture) 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as ...
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Section 12 Timer W TCNT value GRA GRB GRC GRD H'0000 FTIOB FTIOC FTIOD Figure 12.10 shows another example of operation in PWM mode. The output signals and TCNT is cleared at compare match A, and the ...