hi-3210 Holt Integrated Circuits, Inc., hi-3210 Datasheet
hi-3210
Related parts for hi-3210
hi-3210 Summary of contents
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... May 2011 GENERAL DESCRIPTION The HI-3210 from Holt Integrated Circuits is a single chip CMOS data management IC capable of managing, storing and forwarding avionics data messages between eight ARINC 429 receive channels and four ARINC 429 transmit channels. The ARINC 429 buses may be operated independently, ...
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... Interrupt Handler ARINC 429 RECEIVE DATA MEMORY FILTER TABLE FIFO LABEL FILTER EEPROM SPI Auto-Initialization EEPROM HOLT INTEGRATED CIRCUITS 2 Programmable Interrupts ARINC 429 TRANSMITTER 0 ARINC 429 TRANSMIT Descriptor Table 0 SCHEDULER 0 TRANSMIT TIMER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 HI-3210 ...
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... APPLICATION OVERVIEW The HI-3210 is a flexible device for managing ARINC 429 communications and data storage in many avionics applications. The device architecture centers around a 32K x 8 static RAM used for data storage, data filtering tables and table-driven transmission schedulers. Once configured, the device can operate autonomously without a host CPU, negating the need for software development or DO-178 certification ...
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... Descriptor Table 3 RAM HOLT INTEGRATED CIRCUITS 4 HCSB HSCLK SPI HMOSI HMISO AINT ARINC 429 RECEIVE FIFO INTERRUPT AACK CONTROL HI-3210 4 x ARINC 429 Transmit Buses TRANSMIT TRANSMITTER 0 SCHEDULER 0 TRANSMIT TIMER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 HI-3210 Host CPU 4 x ARINC 429 Transmit Buses ...
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... Channel 0, Label FF “ “ “ Channel 0, Label 01 Channel 0, Label 00 EEPROM SPI Auto-Initialization EEPROM HOLT INTEGRATED CIRCUITS 5 TRANSMIT TRANSMITTER 3 SCHEDULER 3 TRANSMIT TIMER 4 x ARINC 429 TRANSMIT Transmit Buses TRANSMITTER 2 SCHEDULER 2 TRANSMIT TIMER TRANSMIT TRANSMITTER 1 SCHEDULER 1 TRANSMIT TIMER TRANSMIT TRANSMITTER 0 SCHEDULER 0 TRANSMIT TIMER HI-3210 ...
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... Programmable event interrupt acknowledge MODE2 through MODE0 define HI-3210 start-up and initialization mode Master Reset to HI-3210 Active High Multiplexed with MODE0 pin, PROG initiates HI-3210 Auto-Initialization EEPROM programming routine READY goes high when post-RESET initialization is complete Master enable signal for ARINC 429 transmit schedulers ...
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... HI-3210 MEMORY MAP 0x8XXX Configuration Registers 0x8000 0x7FFF RESERVED 0x7C00 0x7BFF Look-up Tables 0x7A00 0x79FF RESERVED 0x6000 0x5FFF ARINC 429 TX3 Transmit Schedule 0x5800 0x57FF ARINC 429 TX2 Transmit Schedule 0x5000 0x4FFF ARINC 429 TX1 Transmit Schedule 0x4800 0x47FF ARINC 429 TX0 ...
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... HI-3210 REGISTER MAP ADDRESS R/W REGISTER 0x8000 R* ARINC 429 Rx PENDING INTERRUPT 0x8001 R ARINC 429 Rx INTERRUPT ADDRESS 0 0x8002 R ARINC 429 Rx INTERRUPT ADDRESS 1 0x8003 R ARINC 429 Rx INTERRUPT ADDRESS 2 0x8004 R ARINC 429 Rx INTERRUPT ADDRESS 3 0x8005 R ARINC 429 Rx INTERRUPT ADDRESS 4 0x8006 R ARINC 429 Rx INTERRUPT ADDRESS 5 0x8007 ...
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... R/W PIN ARXBIT7 CONFIG REG 2 0x8070 R BIST CONTROL/STATUS 0x8071 R BIST FAIL ADDRESS [7:0] 0x8072 R BIST FAIL ADDRESS [12:8] 0x8073 R AUTO-INIT FAIL LS ADDRESS [7:0] 0x8074 R AUTO-INIT FAIL MS ADDRESS [15:8] HI-3210 MNEMONIC ARXBIT ARX0CR1 ARX0CR2 ARX1CR1 ARX1CR2 ARX2CR1 ARX2CR2 ARX3CR1 ARX3CR2 ARX4CR1 ARX4CR2 ARX5CR1 ARX5CR2 ARX6CR1 ARX6CR2 ARX7CR1 ...
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... A429TX R/W 0 This bit must be set to a “1” to allow the HI-3210 to transmit ARINC 429 data on any of the four channels. If set to a zero, the HI-3210 will not output ARINC 429 data and the ARINC 429 transmit sequencers will remain in their reset state. ...
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... HI-3210 Operational Status Information The Master Status Register may be read at any time to determine the current operational state of the HI-3210: MASTER STATUS REGISTER (Address 0x800E) Bit Name R/W Default Description 7 READY R 0 This bit is high, when the READY output pin is high, indicating that the part is able to accept and ...
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... ARINC 429 RECEIVE OPERATION The HI-3210 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External analog line receivers handle the physical layer connection ARINC 429 Receive Channel Configuration Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address 0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on ...
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... The eight ARINC 429 RX Control Registers, ARXC0 - 7, define the characteristics of each receive channel. The ARINC 429 receive function of the HI-3210 is acti- vated by setting the A429RX bit in the Master Control Register. When an ARINC 429 message is received by the HI-3210 on any bus checked for protocol compliance ...
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... Transmit scheduler #1 reads any bytes from the block. 0 NEW TX0 R/W 0 This bit is set when a new ARINC 429 word is received and stored in this block reset when the ARINC 429 Transmit scheduler #0 reads any bytes from the block. HI-3210 Label = 0xFF Label = 0x0F 7 Label = 0x07 ...
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... ARINC 429 received message Messages (32-bits) HI-3210 The FIFOs are empty following Reset. All three status registers are cleared. When an ARINC 429 message is written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”. When the FIFO contains more than the user-defined ...
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... This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages 1 AFFF 1 R/W 0 This bit is set to “1” if FIFO #1 contains 32 ARINC 429 messages 0 AFFF 0 R/W 0 This bit is set to “1” if FIFO #0 contains 32 ARINC 429 messages HI-3210 LSB MSB 7 6 ...
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... LSB MSB When in loop-back mode, incoming ARINC 429 messages are ignored by the HI-3210. When running in loop-back mode the ARINC 429 transmit pins may be disabled by pulling the TXMSK input high. This prevents test messages from being output to the external ARINC 429 transmit buses ...
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... Conversely, the data field MSB is bit 31. So the bit significance of the label byte and data fields are opposite. The HI-3210 may be programmed to “flip” the bit ordering of the label byte as soon received and immediately prior to transmission. This is accomplished by setting the AFLIP bit to a “ ...
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... Each pin ARXBIT1 through ARXBIT7 are also specified by a pair of configuration registers similar to ARXBIT0 described above. Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page 9). Note that HI-3210 provides external monitoring of eight bits through pins ARXBIT7 to ARXBIT0. HI-3210 monitor any ARINC 429 received payload bit without performing any host SPI reads ...
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... ARINC 429 TRANSMIT OPERATION The HI-3210 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers such as the Holt HI-8596. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction generated automatically using the four ARINC 429 message schedulers. ...
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... The four pairs of Action and Value bytes describe where the data for each byte may be found. Different op-codes allow the data source to be host CPU populated fixed HI-3210 The user is responsible for construction of the descriptor table and for setting the Repetition Rate prior to asserting RUN/STOP ...
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... Control Register SKIP bit is a zero. If the SKIP bit is a one, the sequencer will wait until the next rollover of the Repetition Rate Counter before starting a new cycle. HI-3210 Current Sequence number ...
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... XXXXXXXX 010 XXXXX LLLLLLLL 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 XXXX XXXXXXXX 111 XXXX XXXXXXXX HI-3210 Op-Code Index LSB MSB MSB ACTION BYTE VALUE BYTE Description End of sequence. When op-code 000 is encountered by the sequencer ...
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... XXXXX LLLLLLLL 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 XXXX XXXXXXXX 111 XXXX XXXXXXXX HI-3210 Op-Code Index LSB MSB MSB ACTION BYTE Description No-Op op-code. ARINC 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table. ...
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... ARINC 429 Immediate Transmit Option The Host CPU may instruct the HI-3210 to transmit an ARINC 429 message immediately using a special SPI command. The SPI command selects the transmit channel and provides the four bytes of data to be sent as a 32-bit ARINC 429 message. ...
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... The RAMFAIL Interrupt is not maskable. 2. Clear Data Memory In Modes and 5, the HI-3210 automatically clears all memory locations in the address range 0x0000 to 0x33FF. This is the space reserved for ARINC 429 message data. Configuration tables and HI-3210 registers are not affected ...
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... Clear data memory Yes (0x0000 - 0x33FF) Initialize Registers and Yes Clear Configuration Tables (0x3400 - 0xFFFF) Auto-Initialize from No EEPROM HI-3210 RESET driven to “1” Stop execution, READY => 0 RESET STATE RESET driven to “0” Sample MODE2:0 inputs MODE 1 MODE 2 MODE 3 No Yes ...
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... There are four fault Interrupt bits in the PIR. Fault Interrupts are not maskable, and their Interrupt Mask bits are fixed at a “1”. COPYERR is set when the HI-3210 detects a mismatch between RAM and EEPROM after attempting to program the Auto-initialization EEPROM. AUTOERR is set when the Auto-Initialization EEPROM ...
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... INT is asserted if this bit is a “1” and the PIR FLAG bit is set 2 ATXRDY R/W 0 INT is asserted if this bit is a “1” and the PIR ATXRDY bit is set 1 - R/W 0 Not Used 0 - R/W 0 Not Used HI-3210 MSB MSB HOLT INTEGRATED CIRCUITS ...
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... RAM BUILT-IN SELF-TEST The HI-3210 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status Register is used to control the BIST function. All tests are destructive, overwriting data present before test commencement. BIST CONTROL/STATUS REGISTER (Address 0x8070) This register controls RAM built-in self-test. Bits 0,1 are Read Only. The remaining bits in this register are Read-Write but can be written only in MODE2:0 = 0x04 ...
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... Device logic asserts this bit when the selected RAM test completes without error. This bit is automatically cleared when RBSTRT bit 3 is set. LOWER BIST FAIL ADDRESS REGISTER (Address 0x8071) UPPER BIST FAIL ADDRESS REGISTER (Address 0x8072) HI-3210 f. Write then read and verify 0x0F g. Write then read and verify 0xF0 h. Write then read and verify 0x00 I. ...
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... SCK signal. There is no configuration setting in the HI-3210 to select SPI Mode 0 or Mode 3 because compatibility is automatic. Beyond this point, the HI-3210 data sheet only shows the SPI Mode 0 SCK signal in timing diagrams. The SPI protocol transfers serial data as 8-bit bytes. Once ...
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... SCK SPI Mode 0 MSB SI Command Byte High FIGURE 2. Single-Byte Read From RAM or a Register SCK SPI Mode 0 MSB SI Command Byte High HI-3210 LSB MSB Data Byte LSB MSB Data Byte 0 FIGURE 3 ...
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... Further, these register addresses will not provide meaningful data in response to read commands. RAM and Register Indirect Addressing Refer to the HI-3210 SPI command set shown in Table 1. SPI commands other than fast-access use an address pointer to indicate the address for read or write transactions. This sixteen-bit memory address pointer (MAP) must be initialized before any non-fast-access read or write operation ...
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... HI-3210 scheduler TT for immediate transmission, where TT represents the channel number. TABLE 1. DEFINED INSTRUCTIONS Number of Data Bytes 1++ Fast Register Read from register RRRR ...
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... IDLE state. Taking the PROG pin low initiates the cycle. The READY pin goes low, and the contents of the HI-3210 memory and registers are copied to the EEPROM. When copying is complete, the HI-3210 executes a byte-by-byte comparison of the EEPROM and its own register / memory contents ...
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... Supply Current Min. Input Voltage (HI) Max. Input Voltage (LO) Pull-Up / Pull-Down Current Min. Output Voltage (HI) Max. Output Voltage (LO) HI-3210 RECOMMENDED CONDITIONS -0 +5 +3.6 V 1.0 W 275°C for 10 sec. 175°C -65°C to +150°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device ...
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... SPI SI Data hold time after SCK rising edge SO high-impedance after CE SCLK SCKH SCKL SCLK SO Hi Impedance HI-3210 SYMBOL SCK clock period inactive between SPI instructions SCK high time SCK low time SO valid after SCK falling edge CE inactive SERIAL INPUT TIMING DIAGRAM t CES t DH MSB ...
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... PIN CONFIGURATION FOR HI-3210, 64-PIN QFN PACKAGE Notes 1 . All VDD and GND pins must be connected. 2. See data sheet page 1 for HI-3210, 64-Pin PQFP Package Configuration. SCANSHIFT HI-3210 AACK 1 ARXBIT6 2 AINT 3 ARXBIT7 4 5 ARX2N 6 ARX3P 7 VDD 8 HI-3210PCx GND 9 ARX3N 10 ARX4P 11 ARX4N 12 ARX5P 13 ...
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... ORDERING INFORMATION HI-3210Px x x PART NUMBER Blank F PART NUMBER PART NUMBER PQ PC HI-3210 PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW -40°C TO +85°C I -55°C TO +125°C T -55°C TO +125°C M PACKAGE ...
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... REVISION HISTORY Document Rev. Date Description of Change DS3210 New 5/10/11 Initial Release. HI-3210 HOLT INTEGRATED CIRCUITS 41 ...
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... BSC SQ (10.00) .055 .002 ± (1.40 ± .05) .004 .002 ± (0.10 ± .05) The metal heat sink pad on the bottom of the package is electrically isolated from the chip. It can be left floating or connected to VDD or GND .281 ± .003 (7.125 ± .075 ) .016 ± .004 (0.40 ± .10 ) .008 typ (0 ...