HI5860IB Intersil, HI5860IB Datasheet
HI5860IB
Specifications of HI5860IB
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HI5860IB Summary of contents
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... HI5860IA* HI5860 IA HI5860IB HI5860IB HI5860IBZ* HI5860IBZ (Note) HI5860SOICEVAL1 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Typical Applications Circuit D11 D10 50Ω BEAD + 10µH 10µF 0.1µF Functional Block Diagram (LSB LATCH D10 (MSB) D11 CLK ...
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Pin Descriptions PIN NUMBER PIN NAME 1 through 12 D11 (MSB) Through D0 (LSB) 13, SLEEP 16 REFLO 17 REFIO 18 FSADJ 19 COMP1 21 IOUTB 22 IOUTA 23 COMP2 20, 25 ACOM 26 DCOM ...
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... SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.3V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150° 0.3V Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C DD Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = DV = +5V (except where otherwise noted +25°C for All Typical Values. A TEST CONDITIONS = 25Ω (Note Internal 1.2V, IOUTFS = 20mA, ...
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Electrical Specifications -40°C to +85° PARAMETER AC CHARACTERISTICS +5V Power Supply f Spurious Free Dynamic Range, f SFDR Within a Window f +5V Power Supply f Total Harmonic Distortion (THD Nyquist f ...
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Electrical Specifications -40°C to +85° PARAMETER +3V Power Supply f Spurious Free Dynamic Range, f SFDR to Nyquist (f /2) CLK +3V Power ...
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Electrical Specifications -40°C to +85° PARAMETER TIMING CHARACTERISTICS Data Set-up Time, t See Figure 4 (Note 3) SU Data Hold Time, t See Figure 4 (Note 3) HLD Propagation Delay Time, t See Figure ...
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Definition of Specifications Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally, the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Full Scale ...
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The same is true for the analog components and the analog ground plane. Consult Application Note 9853. Noise Reduction To minimize power supply ...
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Timing Diagrams CLK D11-D0 I OUT t SETT t PD FIGURE 2. OUTPUT SETTLING TIME DIAGRAM CLK t SU D11-D0 I OUT t PD FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 10 HI5860 50% ...
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Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - -C- α 0.10(0.004) 0.10(0.004 NOTES: 1. These package ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...