hys64d128021 Infineon Technologies Corporation, hys64d128021 Datasheet
hys64d128021
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hys64d128021 Summary of contents
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... – 5 – – 6 – B 200-Pin Small Outline Dual-In-Line Memory Modules ...
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Edition 2003-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... – 5 – – 6 – B 200-Pin Small Outline Dual-In-Line Memory Modules ...
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... HYS64D128021[G/H]BDL–5–B, HYS64D128021[G/H]BDL–6–B, Revision History: Rev. 0.5 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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... Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules 5 Rev. 0.5, 2003-12 ...
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... Description The HYS64D128021[G/H]BDL–5–B and HYS64D128021[G/H]BDL–6–B are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 128M × 64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board ...
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... PC2700S-2533–0–Z two ranks 1 GB SO-DIMM PC3200S–3033–1–Z two ranks 1 GB SO-DIMM PC2700S-2533–0–Z two ranks 1 GB SO-DIMM 7 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules SDRAM Technology 512 MBit (×8) 512 MBit (×8) 512 MBit (×8) 512 MBit (× ...
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... I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select Not Connected Not Usable, reserved for future use 8 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Pin Configuration Rev. 0.5, 2003-12 ...
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... V 126 127 DQ32 128 DQ36 129 DQ33 130 DQ37 V V 131 132 HYS64D128021[H/G]BDL–[5/6]–B Pin Configuration Front side Back side Pin # Symbol Pin # 133 DQS4 134 135 DQ34 136 137 V 138 SS 139 DQ35 140 141 DQ40 ...
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... Table 5 Address Format Density Organization Memory Ranks 128M × 64 1GB 2 Figure 1 Pin Configuration Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules SDRAMs # row/bank/ SDRAMs columns bits 64M × 13/2/11 front side back side 10 Pin Configuration Refresh Period Interval 7.8 µ ...
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... A0-An: SDRAMs D0 - D15 CKE1 CKE: SDRAMs D8 - D15 RAS RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 CKE0 CKE: SDRAMs WE: SDRAMs D0 - D15 Block Diagram - 2 Ranks 128M × 64 DDR SDRAM SO-DIMM HYS64D128021[H/G]BDL–[5/6]–B Figure 2 Data Sheet S1 DQS4 DM4/DQS13 DQS DM S DQS I/O 0 ...
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... DDQ DDQ V V – 0.04 REF V + 0.15 V REF V –0.3 –0.3 V 0.36 V 0.71 1.4 12 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Electrical Characteristics Values Unit Note/ Test typ. max. – DDQ 0.5 – +3.6 V – +3.6 V – +3.6 V °C – +70 °C – ...
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... REF V stabilizes. REF 13 HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Electrical Characteristics Unit Note/Test Condition µA Any input 0 V ≤ All other pins not under test 8) µA DQs are disabled ...
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... IH,MIN IN REF or ≤ IH,MIN IL,MAX for DQ, DQS and DM. ILMAX IN REF IH,MIN RC RAS,MAX OUT 14 HYS64D128021[H/G]BDL–[5/6]–B Electrical Characteristics = V for DQ, DQS and DM. REF Rev. 0.5, 2003-12 Symbol I DD0 I DD1 I DD2P I DD2F I DD2Q I DD3P I DD3N I DD4R I DD4W I DD5 I DD6 I ...
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... Table 9 I Specification for HYS64D128021[H/G]BDL–[5/6]– ×64 2 Ranks –5 Symbol typ. I 1136 DD0 I 1256 DD1 I 48 DD2P I 480 DD2F I 304 DD2Q I 192 DD3P I 672 DD3N I 1296 DD4R I 1336 DD4W I 2296 DD5 I tbd DD6 I 3096 DD7 1) Module I values are calculated on the basis of component DD capacity ...
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... DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Data Sheet HYS64D128021[H/G]BDL–[5/6]–B Small Outline DDR SDRAM Modules Symbol –6 DDR333B Min. Max. Min. ...
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... XSNR t 200 — XSRD t — 7.8 REFI = +2.5 V ± 0.2 V (DDR333 CK/CK slew rate are ≥ 1.0 V/ns. V REF V stabilizes. REF 17 HYS64D128021[H/G]BDL–[5/6]–B Electrical Characteristics –5 Unit Note/ Test Condition DDR400B Min. Max. 0.6 — ns fast slew rate 3)4)5)6)10) 0.7 — ns slow slew rate 3)4)5)6)10) 0.6 — ...
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... For each of the terms, if not already an integer, round to the next highest integer. cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet Small Outline DDR SDRAM Modules V . OL(ac) 18 HYS64D128021[H/G]BDL–[5/6]–B Electrical Characteristics t is equal to the actual system clock CK Rev. 0.5, 2003-12 ...
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... SPD Contents Table 11 SPD Codes for HYS64D128021[H/G]BDL–[5/6]–B Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type (DDR = 07h) 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of DIMM Ranks 6 Data Width (LSB) ...
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... Table 11 SPD Codes for HYS64D128021[H/G]BDL–[5/6]–B Label Code Jedec SPD Revision Byte# Description 22 Component Attributes 23 tCK @ CLmax -0.5 (Byte 18) [ns tAC SDRAM @ CLmax -0.5 [ns] 25 tCK @ CLmax -1 (Byte 18) [ns] 26 tAC SDRAM @ CLmax -1 [ns] 27 tRPmin [ns] 28 tRRDmin [ns] 29 tRCDmin [ns] 30 tRASmin [ns] ...
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... Table 11 SPD Codes for HYS64D128021[H/G]BDL–[5/6]–B Label Code Jedec SPD Revision Byte# Description 72 Module Manufacturer Location 73 Part Number, Char 1 74 Part Number, Char 2 75 Part Number, Char 3 76 Part Number, Char 4 77 Part Number, Char 5 78 Part Number, Char 6 ...
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... Package Outlines (2.15) 1 11.4 ±0.1 (2.45) 1 ±0.1 101 2 MIN. Detail of contacts 0.6 ±0.1 Burnished, no burr allowed Figure 3 Package Outlines – DDR-SDRAM SO-DIMM HYS64D128021[H/G]BDL–[5/6]–B Data Sheet Small Outline DDR SDRAM Modules 67.6 63.6 ±0.1 (2.45) 18.45 ±0.1 1.8 ±0.1 (2.4) 47.4 ±0.1 (2.7) (2.15) 1.5 ±0.1 200 0.45 ±0.03 22 HYS64D128021[H/G]BDL–[5/6]–B Package Outlines 3 ...
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Published by Infineon Technologies AG ...