ICS673M-01 IDT, Integrated Device Technology Inc, ICS673M-01 Datasheet
ICS673M-01
Specifications of ICS673M-01
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ICS673M-01 Summary of contents
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Description The ICS673- low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer ...
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Pin Assignment ...
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Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any ...
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AC Electrical Characteristics VDD = 3.3V ±5%, Ambient Temperature - Parameter Output Clock Frequency (from pin CLK) Input Clock Frequency (into pins REFIN or FBIN) Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, ...
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VCO frequency. The feedback divider begins to miss even more clock edges and the VCO frequency is continually increased until it is running at its maximum frequency. Whether caused by power supply issues or by the external divider, ...
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V below VDD. Hysteresis should be added to the circuit by connecting R4. CHGP VCOIN Figure 2. Using an External Comparator to Reset the ...
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Determining the Loop Filter Values The loop filter components consist of C Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 20 MHz from a 200 kHz input. The phase locked ...
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Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No INDEX AREA Ordering Information Part / Order Number Marking 673M-01ILF 673M-01IL 673M-01ILFT 673M-01IL 673M-01LF 673M-01LF 673M-01LFT 673M-01LF “LF” denotes ...