ICS8305 Integrated Circuit System, ICS8305 Datasheet
ICS8305
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ICS8305 Summary of contents
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... LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the ICS8305 ideal for those applications demanding well de- fined performance and repeatability ...
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... www.icst.com/products/hiperclocks.html 2 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT . ...
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... CLK_EN T D IGURE IMING IAGRAM www.icst.com/products/hiperclocks.html 3 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT ...
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... www.icst.com/products/hiperclocks.html 4 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT 70° ...
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... www.icst.com/products/hiperclocks.html 5 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT ...
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... www.icst.com/products/hiperclocks.html 6 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT 70° ...
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... ORE V DD SCOPE nCLK CLK GND C D EST IRCUIT IFFERENTIAL PART 1 Qx PART ART TO ART www.icst.com/products/hiperclocks.html 7 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT NFORMATION SCOPE UTPUT OAD EST IRCUIT Cross Points I L NPUT EVEL V DDO 2 V DDO ...
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... ROPAGATION ELAY V DDO 2 Q0:Q3 Pulse Width t PERIOD t PW odc = t PERIOD odc & ERIOD 8305AG - KEW TO LVCMOS- -LVCMOS/LVTTL F TO 20% Clock Outputs UTPUT ISE ALL www.icst.com/products/hiperclocks.html 8 ICS8305 D ULTIPLEXED IFFERENTIAL B ANOUT UFFER 80% 80% 20 IME REV. A JUNE 27, 2003 / ...
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... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K CLK V_REF nCLK C1 0. INGLE NDED IGNAL RIVING IFFERENTIAL www.icst.com/products/hiperclocks.html 9 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT UFFER = 3.3V, V_REF should be 1.25V DD I NPUT REV. A JUNE 27, 2003 / ...
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... HiPerClockS Input 3D. H NPUT RIVEN BY IGURE 3.3V R4 125 CLK nCLK HiPerClockS Input NPUT RIVEN OUPLE www.icst.com/products/hiperclocks.html 10 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK/ CLK ...
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... S E CHEMATIC XAMPLE This application note provides general design guide using ICS8305 LVCMOS buffer. Figure 3 shows a schematic example of the ICS8305 LVCMOS clock buffer. In this example, the input VDD VDD Ohm R3 43 3,.3V LVCMOS IGURE XAMPLE 8305AG ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8305 is: 459 8305AG KEW ...
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... ° 0 ° Reference Document: JEDEC Publication 95, MO-153 www.icst.com/products/hiperclocks.html 13 ICS8305 - ULTIPLEXED IFFERENTIAL B ANOUT UFFER m REV. A JUNE 27, 2003 / ...
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... www.icst.com/products/hiperclocks.html 14 ICS8305 - ULTIPLEXED IFFERENTIAL ANOUT ° ...