ICS85408BG ICST [Integrated Circuit Systems], ICS85408BG Datasheet

no-image

ICS85408BG

Manufacturer Part Number
ICS85408BG
Description
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS85408BGILF
Manufacturer:
IDT
Quantity:
20 000
Part Number:
ICS85408BGILFT
Manufacturer:
IDT
Quantity:
20 000
Part Number:
ICS85408BGLF
Manufacturer:
ICS
Quantity:
20 000
Company:
Part Number:
ICS85408BGLFT
Quantity:
286
G
cept most differential input levels and translates them to 3.3V
LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS85408 provides a low power, low
noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make
the ICS85408 ideal for those applications demanding well
defined performance and repeatability.
85408BG
B
HiPerClockS™
ICS
ENERAL
LOCK
nCLK
D
CLK
The ICS85408 is a low skew, high performance
1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClock S ™
family of High Performance Clock Solutions
from ICS. The ICS85408 CLK, nCLK pair can ac-
OE
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
www.icst.com/products/hiperclocks.html
D
IFFERENTIAL
1
F
P
Propagation delay: 2.4ns (maximum)
8 Differential LVDS outputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, HCSL) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
Output skew: 50ps (maximum)
Part-to-part skew: 550ps (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Lead-Free package RoHS compliant
EATURES
IN
A
-
SSIGNMENT
TO
4.4mm x 7.8mm x 0.92mm body package
-LVDS C
24-Lead, 173-MIL TSSOP
nQ6
nQ5
nQ4
nQ3
nQ2
nQ1
Q6
Q5
Q4
Q3
Q2
Q1
ICS85408
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
LOCK
24
23
22
21
20
19
18
17
16
15
14
13
L
D
OW
Q7
nQ7
OE
GND
V
V
GND
V
CLK
nCLK
Q0
nQ0
ISTRIBUTION
DD
DD
DD
ICS85408
S
KEW
REV. A APRIL 25, 2005
, 1-
C
TO
HIP
-8

Related parts for ICS85408BG

ICS85408BG Summary of contents

Page 1

Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS85408 is a low skew, high performance ICS 1-to-8 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS. The ...

Page 2

Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...

Page 3

Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, T STG T 4A ABLE OWER ...

Page 4

Integrated Circuit Systems, Inc. T 4D. LVDS DC C ABLE HARACTERISTICS ...

Page 5

Integrated Circuit Systems, Inc. P ARAMETER 3.3V Power Supply LVDS Float GND + - 3. UTPUT OAD EST IRCUIT PART 1 nQx PART 1 Qx PART 2 nQy PART sk(pp ...

Page 6

Integrated Circuit Systems, Inc. 80% Clock 20% Outputs UTPUT ISE ALL IME V DD LVDS DC Input V S ETUP LVDS DC Input I S ETUP OS 85408BG D - -LVDS ...

Page 7

Integrated Circuit Systems, Inc IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 ...

Page 8

Integrated Circuit Systems, Inc IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show inter- PP ...

Page 9

Integrated Circuit Systems, Inc ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85408 is: 1821 85408BG D - IFFERENTIAL TO R ...

Page 10

Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-153 85408BG D - -LVDS C IFFERENTIAL TO TSSOP EAD ACKAGE IMENSIONS ...

Page 11

Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...

Page 12

Integrated Circuit Systems, Inc ...

Related keywords