ICS8705BY Integrated Device Technology, Inc., ICS8705BY Datasheet
ICS8705BY
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ICS8705BY Summary of contents
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Integrated Circuit Systems, Inc ENERAL ESCRIPTION The ICS8705 is a highly versatile 1:8 Differen- ICS tial-to-LVCMOS/LVTTL Clock Generator and a HiPerClockS™ member of the HiPerClockS™ family of High Per- formance Clock Solutions from ICS. The ICS8705 has two ...
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Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ...
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Integrated Circuit Systems, Inc. T 3A. PLL ABLE NABLE UNCTION ABLE ...
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Integrated Circuit Systems, Inc BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S ...
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Integrated Circuit Systems, Inc ABLE IFFERENTIAL HARACTERISTICS ...
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Integrated Circuit Systems, Inc ABLE OWER UPPLY HARACTERISTICS ...
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Integrated Circuit Systems, Inc ABLE HARACTERISTICS ...
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Integrated Circuit Systems, Inc. P ARAMETER 1.65V± DDA V DDO LVCMOS GND -1.165V±5% 3.3V C /3. ORE UTPUT OAD EST V DD nCLK V Cross Points PP CLK GND D I ...
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Integrated Circuit Systems, Inc. nCLK1 CLK1 FB_IN ➤ ➤ t (Ø) t jit(Ø (Ø) — t (Ø) = Phase Jitter mean t (Ø) = Static Phase Offset mean (where t (Ø) is any random sample, and t (Ø) ...
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Integrated Circuit Systems, Inc OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8705 provides sepa- rate power supplies to isolate any high switching ...
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Integrated Circuit Systems, Inc IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V and V SWING V and V input requirements. Figures show ...
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Integrated Circuit Systems, Inc AYOUT UIDELINE The schematic of the ICS8705 layout example is shown in Figure 4A. The ICS8705 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as ...
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Integrated Circuit Systems, Inc. The following component footprints are used in this layout example: All the resistors and capacitors are size 0603 OWER AND ROUNDING Place the decoupling capacitors as close as possible to the power pins. If ...
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Integrated Circuit Systems, Inc. θ ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data ...
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Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR EAD ABLE ...
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Integrated Circuit Systems, Inc ABLE RDERING NFORMATION ...
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Integrated Circuit Systems, Inc ...