IDT5V9885B Integrated Device Technology, Inc., IDT5V9885B Datasheet
IDT5V9885B
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IDT5V9885B Summary of contents
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... The IDT5V9885B can be programmed through the use of the I JTAG interfaces. The programming interface enables the device to be programmed when normal operation or what is commonly known as in-system programmable ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR FUNCTIONAL BLOCK DIAGRAM XTALOUT OSC. XTALIN/REFIN CLKIN SHUTDOWN/OE GIN5/CLK_SEL Multi-Purpose I/O, Programming, Features 2 I C/JTAG NOTE: 1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting. ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PIN CONFIGURATION CLKIN 1 GND 2 GOUT1/LOSS_CLKIN 3 XTALIN/REFIN 4 XTALOUT 5 OUT1 OUT3 TQFP TOP VIEW 26 25 GIN2/TMS C/JTAG 22 GOUT1/LOSS_CLKIN GIN5/CLK_SEL 21 XTALIN/REFIN GIN1/SCLK/TCLK 20 GIN0/SDA/TDI 19 GND INDUSTRIAL TEMPERATURE RANGE ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PIN DESCRIPTION PF32 NL28 Pin Name Pin# Pin# CLKIN 1 XTALIN/REFIN 4 XTALOUT 5 GIN0/SDAT/TDI 19 GIN1/SCLK/TCK 20 GIN2/TMS 24 GIN3/SUSPEND 27 GIN4/TRST 25 GIN5/CLK_SEL 21 SHUTDOWN/ C/JTAG 22 2 OUT1 6 OUT2 29 OUT3 8 OUT4 10 OUT4 11 OUT5 15 16 OUT5 OUT6 13 GOUT0/TDO/LOSS_LOCK 31 GOUT1/LOSS_CLKIN 3 V 7,12,17, 10,15,20 DD 23,26,32 GND 2,9,14, 2,12,26 18,30 NOTES: 1. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I 2 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR PLL FEATURES AND DESCRIPTIONS D0 Divider VCO M0 Multiplier PLL0 Block Diagram D1 Divider VCO M1 Multiplier PLL1 Block Diagram D2 Divider VCO M2 Multiplier PLL2 Block Diagram 5 INDUSTRIAL TEMPERATURE RANGE Spread Spectrum Modulation Spread Spectrum Modulation ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Pre-Divider (D) Values PLL0 1 - 255 PLL1 1 - 255 PLL2 1 - 255 REFERENCE CLOCK INPUT PINS AND SELECTION The 5V9885B supports up to two clock inputs. One of the clock inputs (XTALIN/ REFIN) can be driven by either an external crystal or a reference clock. The second clock input (CLKIN) can only be driven from an external reference clock ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Feedback-Divider N[11:0] and A[3:0] are the bits used to program the feedback-divider for PLL0 (N0 and A0) and PLL1 (N1 and A1). If spread spectrum generation is enabled for either PLL0 or PLL1, then the SS_OFFSET[5:0] bits (0x61, 0x69) would be factored into the overall feedback divider value. See the SPREAD SPECTRUM GENERATION section for more details on how to configure PLL0 and PLL1 when spread spectrum is enabled ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Note that the actual 10-bit post-divider value has a 2 added to the integer value Q and the outputs are routed through another div/2 block. The post-divider should never be disabled unless the output bank will never be used during normal operation. The output frequency range for LVTTL outputs are from 4.9KHz to 200MHz ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Modulation frequency (Eq. 11) PFD (Eq. 12) VCO PFD NOM Nssc * Tssc) (Eq. 13) SSC PFD Spread: ΣΔ … the number of samples used depends on the N ΣΔ ≤ SS_OFFSET ±Spread% = ΣΔ * 100 64 * (2*N[11:0] + A{3: ± ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Example F = 25MHz 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings. IN OUT Since the spread is center, the SS_OFFSET can be set to '0'. Solve for the nominal M value; keep in mind that the nominal M should be chosen to maximize the VCO ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR The spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the PLL output when the PLL is programmed for fractional divide. The following is an example of how to set the fractional divider. ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR LOOP FILTER The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide loop bandwidth is best for low jitter generation ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows. Phase Margin: ω (Rz * Cz) (Eq. 23) ω (Eq. 24 φm = (360 / 2π [tan (ωc/ ωz) - tan (ωc/ ωp ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR CONFIGURING THE MULTI-PURPOSE I/Os The 5V9885B can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I (GIN0, GIN1, GIN2, GIN3, GIN4, GIN5) have different uses depending on the mode of operation. The four available modes of operation are: ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MODE2 - Manual Frequency Control (MFC) Mode for all PLLs In this mode, the configuration of PLL0, PLL1, and PLL2 can be changed during operation. The GINx pins are used to control the selection four different Dx, Mx, P, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3 become configuration selection pins for D1 and M1 of PLL1, and GIN4 and GIN5 become configuration selection pins for D2 and M2 of PLL2 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Understanding the GIN Signals During power up, the part will virtually be in MFC mode2, therefore, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the I This means that when in programming mode, the PLL configuration can only be changed by writing directly to the registers of the currently selected configuration. ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM PLL0 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL1 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL2 Prescaler " ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM PLL0 Prescaler "D" CONFIG0 CONFIG1 CONFIG2 CONFIG3 Multiplier "M" CONFIG0 CONFIG1 CONFIG2 CONFIG3 PLL1 Prescaler "D" CONFIG0 CONFIG4 CONFIG5 Multiplier "M" CONFIG0 CONFIG4 CONFIG5 PLL2 Prescaler "D" ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR BLOCK DIAGRAM FOR SHUTDOWN/OE CONTROL SIGNAL MUX SHUTDOWN/OE NOTE: This illustration shows the internal logic behind the SHUTDOWN/OE pin and the bits associated with it. PM2 OE1 OE2 OE3 PM3 01 10 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR POWER UP AND POWER SAVING FEATURES If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete power down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal GINx signals via the enable bits at memory address 0x05 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR Revertive The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary clock cycles. LOSS_LOCK and LOSS_CLKIN signals will be asserted. LOSS_LOCK will remain asserted until the PLL achieves lock, as previously defined, to the new input clock ...
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... PROGRAMMING THE DEVICE I C and JTAG may be used to program the 5V9885B. The LOW for I C mode. 2 Hardwired Parameters for the IDT5V9885B JTAG identification number = 32'b0000_0000001110101100_00000110011_1 Device (slave) address = 7'b1101010 ID Byte for the 5V9885B = 8'b00010000 I C PROGRAMMING 2 The 5V9885B is programmed through an I byte of data after a write frame to the correct slave address is interpreted as the register address ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR EXTERNAL I C INTERFACE CONDITION 2 KEY: From Master to Slave From Master to Slave, but can be omitted if followed by the correct sequence Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can generate a repeated START condition, and address another Slave address without first generating a STOP condition ...
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... C, only two bytes are transferred. The Device Address is issued with the read/write bit set to "0", followed by the appropriate command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V9885B will not generate Acknowledge bits ...
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... EEPROM PROGRAMMABLE CLOCK GENERATOR In order for the save and restore instructions to function properly, the IDT5V9885B must not be in shutdown mode (SHUTDOWN pin asserted). In the event of an interrupt of some sort such as a power down of the part in the middle of a save or restore operation, the contents to or from the EEPROM will be partially loaded, and a CRC error will be generated ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR I C BUS DC CHARACTERISTICS 2 Symbol Parameter V Input HIGH Level IH V Input LOW Level IL V Hysteresis of Inputs HYS I Input Leakage Current IN V Output LOW Voltage BUS AC CHARACTERISTICS FOR STANDARD MODE 2 Symbol Parameter F Serial Clock Frequency (SCLK) SCLK ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Symbol Description V Internal Power Supply Voltage DD V Input Voltage I (2) V Output Voltage O T Junction Temperature J T Storage Temperature STG NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter V Input HIGH Voltage Level (1) IHH V Input MID Voltage Level (1) IMM V Input LOW Voltage Level (1) ILL I 3-Level Input DC Current 3 I Total Power Supply Current DD (3.3V Supply Total Power Supply Current in ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR DC ELECTRICAL CHARACTERISTICS FOR LVDS Symbol Parameter V (+) Differential Output Voltage for the TRUE binary state OT V (-) Differential Output Voltage for the FALSE binary state OT Δ V Change in V between Complimentary Output States Output Common Mode Voltage (Offset Voltage) OS Δ ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR AC TIMING ELECTRICAL CHARACTERISTICS (SPREAD SPECTRUM GENERATION = OFF) Symbol Parameter f Input Frequency IN 1/t1 Output Frequency f VCO Frequency VCO f PFD Frequency PFD f Loop Bandwidth BW t2 Input Duty Cycle t3 Output Duty Cycle Slew Rate SLEWx(bits Slew Rate t4 SLEWx(bits (2) Slew Rate ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR TEST CIRCUITS AND CONDITIONS V DD 0.1μF NOTE: 1. All V pins must be tied together. DD OTHER TERMINATION SCHEME (BLOCK DIAGRAM) OUTPUTS GND LVTTL: -15pF for each output OUTPUTS GND LVPECL Ω Ω Ω Ω Ω -2V for each output with 5pF ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default Register ADDR Hex Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default Register ADDR Hex Value OEM1[1; 0x1F ODIV1_CONFIG0 0x20 ODIV1_CONFIG1 0x21 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default ADDR Register 7 Hex Value 0x40 0x41 0x42 0x43 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RAM (PROGRAMMING REGISTER) TABLES BIT # (Default Settings) Default ADDR Register 7 Hex Value 0x60 DITH0 0x61 0x62 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR RECOMMENDED LANDING PATTERN NOTE: All dimensions are in millimeters. INDUSTRIAL TEMPERATURE RANGE NL 28 pin 36 ...
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... IDT5V9885B 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR ORDERING INFORMATION XXXXX XX X IDT Package Process Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 INDUSTRIAL TEMPERATURE RANGE Industrial (-40°C to +85°C) I Thin Quad Flat Pack - Green PFG NLG Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package - Green 5V9885B 3 ...