IDT70T633 Integrated Device Technology, IDT70T633 Datasheet
IDT70T633
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IDT70T633 Summary of contents
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... Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device for BUSY output flag on Master, ◆ ...
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... High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Description The IDT70T633 high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM combination MAS- TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Pin Configuration (1,2,3) 03/13/ TDI NC 17L TDO A 18L I 16L I I/O I 10R 10L DDQL I/O NC I/O V 11L 11R DDQL ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Pin Configurations (1,2,3,8) 03/13/ DDQR I I I/O 6 10L I/O 7 10R I/O 8 11L I/O 9 11R V 10 DDQL I/O 12 12L I/O 13 12R V 14 DDQR DDQL I/O 22 13R ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Pin Configurations (1,2,3) 03/12/ I TDO TDI I DDQR I 10L E V I/O I/O NC 11L I 11R I 12L ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Pin Names Left Port Right Port CE CE Chip Enables (Input R/W R/W Read/Write Enable (Input Output Enable (Input (1) ( Address (Input) 0L 18L 0R 18R I/O - I/O I/O - I/O Data Input/Output 0L 17L 0R 17R ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Truth Table I—Read/Write and Enable Control OE SEM ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Recommended Operating Temperature and Supply Voltage Ambient Grade Temperature O O Commercial + Industrial - +85 C NOTE: 1. This is the parameter T . This is the "instant on" case temperature. A Absolute Maximum Ratings Symbol Rating V V Terminal Voltage ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current JTAG & ZZ Input Leakage Current LI (1, Output Leakage Current LO (1) V (3.3V) Output Low Voltage OL (1) V (3.3V) Output High Voltage ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM AC Test Conditions (V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 4 3.5 3 ∆ 2 ACE 2 (Typical, ns) 1 3.3V/2.5V) DDQ GND to 3.0V / GND to 2.5V 2ns Max. 1.5V/1.25V 1.5V/1.25V Figure 1 5670 tbl 11 50Ω ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE UB. 2. Timing depends on which signal is de-asserted first CE, OE UB. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY 3 ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM (9) UB R/W DATA OUT DATA IN Timing Waveform of Write Cycle No Controlled Timing ADDRESS ( SEM ( (9) UB, LB R/W DATA IN NOTES during all address transitions ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM RapidWrite Mode Write Cycle Unlike other vendors' Asynchronous Random Access Memories, the IDT70T651/9 is capable of performing multiple back-to-back write operations without having to pulse the R/W, CE, or BEn signals high during address transitions. This RapidWrite Mode functionality allows the ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM AC Electrical Characteristics over the Operating Temperature Range and Supply Voltage Range for RapidWrite Mode Write Cycle Symbol t Allowable Address Skew for RapidWrite Mode AAS t Address Rise/Fall Time for RapidWrite Mode ARF NOTE: 1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle. ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM (1) I R/W OE NOTES and are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (3) (2) t APS CE "B" (3) BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1,3,4) IH ADDR "A" ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" (3) R/W "A" INT "B" ADDR "B" CE "B" (3) OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1. 2. There are eight semaphore flags written to via I SEM = V ...
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... BUSY signal as a write inhibit signal. Thus on the IDT70T633/1 RAM the BUSY pin is an output if the part is used and the BUSY pin is an input if the part used master (M/S pin = V ...
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... The eight semaphore flags reside within the IDT70T633 separate memory space from the Dual-Port RAM array. This address space is accessed by placing a low input on the SEM pin (which acts as ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 24 ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Sleep Mode The IDT70T633/1 is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will have the lowest possible power consumption ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70T631 is 0x33C. Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) ...
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... IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTES: 1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only 2. Green parts available. For specific speeds, packages and poweres contact your local sales office. ...