IDT70V05 Integrated Device Technology, IDT70V05 Datasheet

IDT70V05

Manufacturer Part Number

IDT70V05

Description

High-speed 3.3v 8k X 8 Dual-port Static Ram

Manufacturer

Integrated Device Technology

Datasheet

1.IDT70V05.pdf (22 pages)

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Download datasheet (163Kb)

Features

◆ ◆ ◆ ◆ ◆

Functional Block Diagram

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

I/O

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20ns (max.)

Low-power operation

– IDT70V05S

– IDT70V05L

IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

BUSY

- I/O

SEM

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

Active: 380mW (typ.)

Standby: 660 µ W (typ.)

R/W

INT

12L

(1,2)

(2)

Decoder

Address

R/W

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Control

I/O

ARBITRATION

SEMAPHORE

INTERRUPT

MEMORY

ARRAY

LOGIC

M/S

◆ ◆ ◆ ◆ ◆

one device

M/S = V

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Control

I/O

for BUSY input on Slave

for BUSY output flag on Master

Decoder

Address

R/W

IDT70V05S/L

JULY 2006

2942 drw 01

R/W

I/O

BUSY

SEM

INT

12R

(2)

-I/O

DSC 2941/8

(1,2)

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