IDT70V05S Integrated Device Technology, IDT70V05S Datasheet
IDT70V05S
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IDT70V05S Summary of contents
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... True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) Low-power operation – IDT70V05S Active: 400mW (typ.) Standby: 3.3mW (typ.) – IDT70V05L Active: 380mW (typ.) Standby: 660 W (typ.) IDT70V05 easily expands data bus width to 16 bits or more ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM The IDT70V05 is a high-speed Dual-Port Static RAM. The IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port SRAM combination MASTER/SLAVE Dual-Port SRAM for 16-bit- or-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM 11L A 10L 12L N/C N SEM R I/O N I INDEX NOTES: 1. All V pins must be connected to power supply. ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM (1) Inputs SEM NOTE — — 12L 0R 12R (1) Inputs SEM NOTE: 1. There are eight semaphore flags written to via I/O ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias Storage T STG Temperature I DC Output OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol Parameter CE I Dynamic Operating = V , Outputs Open CC IL SEM Current = V IH (3) (Both Ports Active MAX Standby Current = SB1 R L SEM SEM (Both Ports - TTL = R (3) Level Inputs MAX Standby Current or SB2 ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Military, Industrial and Commercial Temperature Ranges GND to 3.0V 3ns Max. DATA OUT BUSY 1.5V INT 435 1.5V Figures 1 and 2 2941 tbl 10 Figure 1 ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) t Output Low-Z Time LZ (1,2) t Output High-Z Time ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first CE or OE. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no 3 ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM ADDRESS OE (9) CE SEM or ( (4) DATA OUT DATA IN ADDRESS (9) CE SEM or ( DATA IN NOTES must be HIGH during all address transitions LOW CE and a LOW R/W for memory array writing cycle write occurs during the overlap (t ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE for the duration of the above timing (both write and read cycle “DATA VALID” represents all I/O's (I/O -I/O OUT 0 A (2) SIDE "A" ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable LOW t BAC BUSY Dis able Time from Chip Enable HIGH ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins IL. ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM W R/ "A" BUSY "B" "B" NOTES: must be met for both BUSY input (slave) and output (master BUSY is asserted on port “B” Blocking R/W “B” only for the slave version. ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM ADDR "A" "A" "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM Left Port 12L 1FFF 1FFE NOTES: 1. Assumes BUSY = BUSY = BUSY = V , then no change BUSY = V , then no change Inputs Outputs A -A 12L ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM BUSY (L) Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs. The IDT70V05 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or accessed, at the same time with the only possible conflict arising from the simultaneous writing of simultaneous READ/WRITE of, a non- semaphore location ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token ...
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... IDT70V05S/L High-Speed Dual-Port Static RAM IDT XXXXX A 999 Device Power Speed Type 3/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 and 3 Added additional notes to pin configurations 6/9/99: Changed drawing format 11/10/99: Replaced IDT logo 3/10/00: Added 15 & 20ns speed grades ...