IDT70V07 Integrated Device Technology, IDT70V07 Datasheet
IDT70V07
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IDT70V07 Summary of contents
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... Integrated Device Technology, Inc. HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM ◆ ◆ ◆ ◆ ◆ IDT70V07 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ M ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Description The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 16-bit- or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...
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... PN80-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. (con't IDT70V07PF (4) PN80-1 80-Pin TQFP (5) Top View ...
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... This text does not indicate orientation of the actual part-marking. (con't BUSY M INT GND BUSY IDT70V07G (4) G68-1 68-Pin PGA (5) Top View GND GND I I/O I/O I/O 5L ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs CE OE SEM R NOTE: ≠ — A — 14L 0R 14R Truth Table II: Semaphore Read/Write Control (1) Inputs CE OE SEM R ↑ ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE < 2.0V, input leakages are undefined. ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first OE. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no 3 ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM ( R DATA OUT DATA IN Timing Waveform of Write Cycle No Controlled Timing ADDRESS ( SEM ( R/W DATA IN NOTES must be HIGH during all address transitions. ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE NOTES for the duration of the above timing (both write and read cycle “DATA VALID” represents all I/O's (I/O ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable t BAC ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (SLAVE) and output (MASTER BUSY is asserted on Port "B" blocking R/W "B" Waveform of BUSY Arbitration Controlled by CE Timing ADDR " ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTE: 1. 'X' in part number indicates power rating (S or L). ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V07 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and is not met, either BUSY enable inputs of this port ...
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... V per Truth master, use the BUSY signal as a write inhibit signal. Thus on the IDT70V07 RAM the BUSY pin is an output if the part is used as a master (M/S pin = slave (M/S pin = two or more master parts were used when expanding in width, a ...
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... The eight semaphore flags reside within the IDT70V07 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts ...
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... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT70V07’s Dual-Port SRAM. Say the 32K x 8 SRAM was to be divided into two 16K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. ...
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... IDT70V07S/L High-Speed 32K x 8 Dual-Port Static RAM Ordering Information IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Datasheet Document History: 3/24/99: Initiated datasheet document history Converted to new format ...