IDT70V24 IDT [Integrated Device Technology], IDT70V24 Datasheet
IDT70V24
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IDT70V24 Summary of contents
Page 1
... BUSY outputs and INT outputs are non-tri-stated push-pull. ©2000 Integrated Device Technology, Inc. HIGH-SPEED 3. DUAL-PORT STATIC RAM IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M M BUSY and Interrupt Flag ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM The IDT70V24 is a high-speed Dual-Port Static RAM. The IDT70V24 is designed to be used as a stand-alone 64K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic ...
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... OE SEM I/O I/O I I/O I/O I GND V R IDT70V24G (4) G84-3 74 GND 84-Pin PGA (5) Top View SEM GND GND I/O I/O I/O 10R 13R 15R ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM (1) Inputs NOTE — — 11L 0R 11R Inputs ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol Rating (2) V Terminal Voltage TERM with Respect to GND Temperature T BIAS Under Bias Storage T STG Temperature I DC Output OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol Parameter CE I Dynamic Operating = V , Outputs Open CC IL SEM Current = V IH (3) (Both Ports Active MAX Standby Current SB1 and R SEM SEM (Both Ports - TTL = R (3) Level Inputs MAX CE I Standby Current = V SB2 " ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Industrial and Commercial Temperature Ranges GND to 3.0V 3ns Max. 1.5V DATA OUT BUSY NT 1.5V I 435 Figures 1 and 2 2911 tbl 10 Figure 1. AC Output Test Load ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE (3) t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation 3 ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM ADDRESS OE CE SEM ( SEM ( (4) DATA OUT DATA IN ADDRESS (9) CE SEM DATA IN NOTES & LB must be high during all address transitions low and a LOW CE and a LOW R/W for memory array writing cycle. ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM VALID ADDRESS SEM I NOTES & for the duration of the above timing (both write and read cycle “DATA VALID” represents all I/O's (I/O -I/O OUT 0 A (2) SIDE "A" ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol Parameter BUSY TIMING ( BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable LOW t BAC BUSY Disable Time from Chip Enable HIGH ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM R/ W "A" BUSY "B" "B" NOTES: must be met for both BUSY input (slave) and output (master until BUSY 2. Busy is asserted on port "B" blocking R/W "B" only for the “slave” version. ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM ADDR "A" ( "A" "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V24 are push L R pull, not open drain outputs. On slaves the BUSY input internally inhibits writes the inputs to the opposite port were stable prior to the address and enable inputs of this port not met, either BUSY enable inputs of this port ...
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... High-Speed Dual-Port Static RAM BUSY L Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V24 SRAMs. The IDT70V24 provides two ports with separate control, address and I/O pins that permit independent access to any location in memory. The IDT70V24 has an automatic power down feature controlled by CE. ...
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... The eight semaphore flags reside within the IDT70V24 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as ...
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... Perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT70V24’s Dual-Port SRAM. Say the SRAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. ...
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... IDT70V24S/L High-Speed Dual-Port Static RAM IDT XXXXX A 999 Device Power Speed Package Type 3/8/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations 6/10/99: Changed drawing format 8/1/99: Page 2 TQFP for corrected pinout (no pin 55 was shown) ...