IDT70V28L Integrated Device Technology, IDT70V28L Datasheet

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IDT70V28L

Manufacturer Part Number
IDT70V28L
Description
High-speed 3.3v 64k X 16 Dual-port Static Ram
Manufacturer
Integrated Device Technology
Datasheet

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©2002 Integrated Device Technology, Inc.
NOTES:
1. BUSY is an input as a Slave (M/S=V
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V28L
Dual chip enables allow for depth expansion without
external logic
IDT70V28 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
I/O
Active: 440mW (typ.)
Standby: 660µW (typ.)
BUSY
I/O
SEM
R/
CE
CE
8-15L
INT
A
OE
UB
LB
0-7L
A
15L
W
0L
0L
1L
L
L
L
L
L
L
L
(1,2)
(2)
IL
Decoder
Address
) and an output when it is a Master (M/S=V
R/W
CE
CE
OE
0L
1L
L
L
16
HIGH-SPEED 3.3V
64K x 16 DUAL-PORT
STATIC RAM
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
64Kx16
70V28
LOGIC
M/S
IH
1
).
(1)
M/S = V
M/S = V
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Control
I/O
IL
IH
for BUSY input on Slave
for BUSY output flag on Master,
16
Decoder
Address
CE
CE
OE
R/W
0R
1R
R
R
4849 drw 01
IDT70V28L
R/
UB
CE
CE
OE
LB
BUSY
A
A
SEM
INT
I/O
I/O
15R
0R
W
R
R
0R
1R
R
R
R
8-15R
0-7R
R
(2)
DSC-4849/3
R
(1,2)

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IDT70V28L Summary of contents

Page 1

... High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V28L Active: 440mW (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth expansion without external logic IDT70V28 easily expands data bus width to 32 bits or ...

Page 2

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM The IDT70V28 is a high-speed 64K x 16 Dual-Port Static RAM. The IDT70V28 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word system. Using the IDT MASTER/SLAVE Dual- ...

Page 3

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Left Port Right Port Chip Enables R/W R/W Read/Write Enable Output Enable Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output 0L 15L 0R 15R SEM SEM Semaphore Enable Upper Byte Select ...

Page 4

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM < 0. >V -0.2V CC (3) X NOTES: 1. Chip Enable references are shown above with the actual and ' CMOS standby requires ' either < 0.2V or >V (1) Inputs ...

Page 5

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTES: < Vcc 2.0V, input leakages are undefined. Chip Enable 2. Refer to Truth Table Symbol Parameter I Dynamic Operating ...

Page 6

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load ADDR ( UB, LB R/W DATA OUT BUSY OUT CE ( NOTES: 1. Timing depends on which signal is asserted last, OE, CE UB. ...

Page 7

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) t Output Low-Z Time ...

Page 8

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM ADDRESS OE (9,10 SEM ( ( R/W DATA OUT DATA IN ADDRESS (9,10 SEM ( ( R/W DATA IN NOTES and during all address transitions write occurs during the overlap ( ...

Page 9

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM VALID ADDRESS t AW SEM I R/W OE NOTES and for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table "DATA VALID" represents all I/O's (I/O - I/O OUT ...

Page 10

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low t BAC BUSY Access Time from Chip Enable High t BDC ...

Page 11

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins refer to Chip Enable Truth Table. ...

Page 12

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM BUSY ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" BUSY S ADDR "A" t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 13

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM ADDR "A" CE "A" "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 14

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM BUSY Inputs Outputs 15L CE CE BUSY ( 15R MATCH MATCH MATCH MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V28 are push- ...

Page 15

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed ...

Page 16

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM verifies its success in setting the latch by reading it was successful, it proceeds to assume control over the shared resource was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’ ...

Page 17

... IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers. 8/01/99: Initial Public Offering 1/10/01: Page 3 Increased storage temperature parameter Clarified T A Page 5 DC Electrical parameters–changed wording from "open" to "disabled" ...

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