IDT71T75702 IDT [Integrated Device Technology], IDT71T75702 Datasheet

IDT71T75702

Manufacturer Part Number

IDT71T75702

Description

512K x 36, 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs

Manufacturer

IDT [Integrated Device Technology]

Datasheet

1.IDT71T75702.pdf (26 pages)

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(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.

They are designed to eliminate dead bus cycles when turning the bus

around between reads and writes, or writes and reads. Thus they have

been given the name ZBT

cycle, and on the next clock cycle the associated data cycle occurs, be

it read or write.

CLK

I/O

ADV/

TMS

TDI

TCK

TDO

512K x 36, 1M x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W W W W W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW

Three chip enables for simple depth expansion

2.5V power supply (±5%)

2.5V (±5%) I/O Supply (V

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit

Address and control signals are applied to the SRAM during one clock

-A

-I/O

, CE

, V

DDQ

, I/O

Feature - No dead cycles between write and read cycles

-I/O

, or Zero Bus Turnaround.

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input/Output

Core Power, I/O Power

Ground

- BW

)

) control (May tie active)

512K x 36, 1M x 18

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Flow-Through Outputs

registers. The outputs are flow-through (no output data register). Output

enable is the only asynchronous signal and can be used to disable the

outputs at any given time.

to be suspended as long as necessary. All synchronous inputs are

ignored when CEN is high and the internal device registers will hold their

previous values.

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state one cycle after the chip is deselected or a write

is initiated.

mode, the IDT71T75702/902 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADV/LD = LOW) or increment the internal burst counter

(ADV/LD = HIGH).

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm

100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array

(BGA).

user to deselect the device when desired. If any one of these three is not

The IDT71T75702/902 contain address, data-in and control signal

A Clock Enable (CEN) pin allows operation of the IDT71T75702/902

There are three chip enable pins (CE

The IDT71T75702/902 have an on-chip burst counter. In the burst

The IDT71T75702/902 SRAMs utilize IDT’s high-performance

Supply

Output

Input

I/O

, CE

IDT71T75702

IDT71T75902

Asynchronous

, CE

Synchronous

Static

N/A

) that allow the

DSC-5319/08

5319 tbl 01

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