IDT71T75702S85PFG IDT, Integrated Device Technology Inc, IDT71T75702S85PFG Datasheet

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IDT71T75702S85PFG

Manufacturer Part Number
IDT71T75702S85PFG
Description
IC SRAM 18MBIT 85NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT71T75702S75PF8.pdf (26 pages)

Specifications of IDT71T75702S85PFG

Format - Memory
RAM
Memory Type
SRAM - Synchronous ZBT
Memory Size
18M (512K x 36)
Speed
85ns
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
71T75702S85PFG

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Part Number:
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
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Part Number:
IDT71T75702S85PFG8
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IDT, Integrated Device Technology Inc
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Part Number:
IDT71T75702S85PFGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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©2004 Integrated Device Technology, Inc.
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
R/
CLK
I/O
A
ADV/
TMS
TDI
TCK
TDO
ZZ
V
V
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W W W W W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (V
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
Address and control signals are applied to the SRAM during one clock
0
DD
SS
-A
0
1
1
-I/O
, CE
, V
,
19
TM
DDQ
31
2
, I/O
,
2
Feature - No dead cycles between write and read cycles
,
P1
2
3
-I/O
,
P4
4
OE
OE
OE
OE
TM
BW
BW
BW
BW
, or Zero Bus Turnaround.
DDQ
1
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address/Load New Address
Linear/Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
- BW
BW
BW
BW
BW
)
4
) control (May tie active)
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
1
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
to be suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
user to deselect the device when desired. If any one of these three is not
The IDT71T75702/902 contain address, data-in and control signal
A Clock Enable (CEN) pin allows operation of the IDT71T75702/902
There are three chip enable pins (CE
The IDT71T75702/902 have an on-chip burst counter. In the burst
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
Supply
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
1
, CE
2
IDT71T75702
IDT71T75902
Asynchronous
Asynchronous
, CE
FEBRUARY 2009
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Static
Static
Static
N/A
N/A
N/A
N/A
N/A
2
) that allow the
DSC-5319/08
5319 tbl 01

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IDT71T75702S85PFG Summary of contents

Page 1

... There are three chip enable pins (CE user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip is deselected or a write is initiated ...

Page 2

... R/ signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place one clock cycle later. is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged ...

Page 3

... Address A [0:18 R/W CEN ADV/LD BWx Clock OE TMS TDI JTAG TCK TRST (optional Control Logic Clk TDO 6.42 3 Commercial and Industrial Temperature Ranges 512K x 36 BIT MEMORY ARRAY Address Control DI DO Mux Sel Gate Data I/O [0:31], I/O P[1:4] 5319 drw 01 , ...

Page 4

... V 2.5 2.625 ____ V +0 (2) ____ V +0.3 V DDQ (1) ____ 0.7 V 5319 tbl 03 /2, once per cycle. CYC 6.42 4 Commercial and Industrial Temperature Ranges BIT MEMORY ARRAY Address Control DI DO Mux Sel Gate Data I/O [0:15], I/O P[1:2] 5319 drw 01a , ...

Page 5

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Ambient Grade V SS (1) Temperature Commerical 0 °C to +70 °C OV Industrial -40 °C to +85 °C OV ...

Page 6

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs 100 ...

Page 7

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs ...

Page 8

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs , (5) R/ ADV ...

Page 9

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps ...

Page 10

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Cycle Address R/ ADV n n n+3 X ...

Page 11

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Cycle Address R/ ADV n NOTES High ...

Page 12

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Cycle Address R/ ADV n n n+3 X ...

Page 13

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Cycle Address R/ ADV ...

Page 14

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Symbol Parameter |I | Input Leakage Current LI , JTAG and ZZ Input Leakage Current | ...

Page 15

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t ...

Page 16

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 17

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 18

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 19

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs CEN Commercial and Industrial Temperature Ranges 6. ...

Page 20

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs CS Commercial and Industrial Temperature Ranges 6. ...

Page 21

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. ...

Page 22

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Instruction ...

Page 23

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 23 ...

Page 24

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 24 ...

Page 25

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs OE OE DATA OUT NOTE read operation is assumed progress. XXXX S XX Device Power ...

Page 26

IDT71T75702, IDT71T75902, 512K x 36 18, 2.5V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter and Flow-Through Outputs Rev Date Pages 0 05/25/00 1 08/24/ 10/16/ 12/21/01 ...

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