IDT71V2556S Integrated Device Technology, IDT71V2556S Datasheet

IDT71V2556S

Manufacturer Part Number

IDT71V2556S

Description

128k X 36, 256k X 18 3.3v Synchronous Zbt Srams 2.5v I/o, Burst Counter Pipelined Outputs

Manufacturer

Integrated Device Technology

Datasheet

1.IDT71V2556S.pdf (28 pages)

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◆ ◆ ◆ ◆ ◆

Features

Description

bit) synchronous SRAMS. They are designed to eliminate dead bus cycles

when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT

Turnaround.

Pin Description Summary

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

ZBT

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W W W W W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (V

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

Address and control signals are applied to the SRAM during one clock

R/W

CLK

I/O

CEN

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

-A

-I/O

, CE

, V

, BW

DDQ

Feature - No dead cycles between write and read

, I/O

, CE

, BW

-I/O

, BW

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Linear / Interleaved Burst Order

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Address Inputs

Advance burst address / Load new address

Test Mode Select

Test Data Input

Test Clock

Test Data Output

- BW

) control (May tie active)

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

DDQ)

, or Zero Bus

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

be suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

the IDT71V2556/58 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO input pin. The LBO pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2556/58 contain data I/O, address and control signal

A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to

There are three chip enable pins (CE

The IDT71V2556/58 has an on-chip burst counter. In the burst mode,

The IDT71V2556/58 SRAMs utilize IDT's latest high-performance

Supply

Output

Input

I/O

IDT71V2556SA/XSA

IDT71V2558SA/XSA

IDT71V2556S/XS

IDT71V2558S/XS

, CE

Asynchronous

Synchronous

FEBRUARY 2007

Static

N/A

, CE

) that allow the user

4875 tbl 01

DSC-4875/09

Related parts for IDT71V2556S

IDT71V2556S Summary of contents

Page 1

... Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input I/O Supply Supply 1 IDT71V2556S/XS IDT71V2558S/XS IDT71V2556SA/XSA IDT71V2558SA/XSA , that allow the user Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Static Synchronous Synchronous N/A Synchronous Asynchronous ...

Page 2

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs (1) Pin Definitions Symbol Pin Function I Address Inputs ADV/LD Advance / Load I R/W ...

Page 3

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST ...

Page 4

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:17] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST ...

Page 5

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage Grade Temperature V (1) SS Commercial 0°C to +70°C 0V Industrial -40°C to +85°C ...

Page 6

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 256K x 18 100 ...

Page 7

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 128K x 36, 119 BGA DDQ I ...

Page 8

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 128K x 36, 165 fBGA (2) CE1 ...

Page 9

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Synchronous Truth Table (5) CEN R/W Chip ADV/LD Enable L L Select Select ...

Page 10

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Interleaved Burst Sequence Table First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst ...

Page 11

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Device Operation - Showint Mixed Load, Burst, Deselect and NOOP Cycles Cycle Address R/W ADV/ ...

Page 12

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation Cycle Address R/W ADV ...

Page 13

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Clock Enable Used Cycle Address R/W ADV/ n n+2 ...

Page 14

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Chip Enable Used Cycle Address R/W ADV/ n n+2 A ...

Page 15

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI |I ...

Page 16

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs AC Electrical Characteristics (V = 3.3V±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) ...

Page 17

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Read Cycle Commercial and Industrial Temperature Ranges (1,2,3,4) 6. ...

Page 18

NOTES represents the first input to the external address the base address A , etc. where address bits A and A are advancing for the four word burst in the ...

Page 19

NOTES represents the first output from the external address timing transitions are identical but inverted to the CE and Individual Byte Write signals (BWx) must be valid on ...

Page 20

NOTES represents the first output from the external address timing transitions are identical but inverted to the CE and CEN when sampled high on ...

Page 21

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CS Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 6. ...

Page 22

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ...

Page 23

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ...

Page 24

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 100 Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 24 ...

Page 25

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 119 Ball Grid Array (BGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 25 ...

Page 26

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 26 ...

Page 27

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation OE DATA OUT NOTE read operation is assumed progress. Ordering ...

Page 28

... Silver Creek Valley Rd San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. Commercial and Industrial Temperature Ranges Updated to new format ...

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