IDT71V3577S75BG IDT, Integrated Device Technology Inc, IDT71V3577S75BG Datasheet

no-image

IDT71V3577S75BG

Manufacturer Part Number
IDT71V3577S75BG
Description
IC SRAM 4MBIT 75NS 119BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71V3577S75BG

Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
4M (128K x 36)
Speed
75ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
119-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71V3577S75BG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT71V3577S75BG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3577S75BG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT71V3577S75BG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3577S75BGG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3577S75BGG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT71V3577S75BGGI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Features
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
Pin Description Summary
NOTE:
1. BW
©2004 Integrated Device Technology, Inc.
CS
CLK
I/O
A
CE
OE
GW
BWE
BW
ADV
ADSC
ADSP
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
V
V
0
DD
SS
-A
0
0
128K x 36, 256K x 18 memory configurations
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Commercial and Industrial:
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
1
-I/O
, CS
, V
, BW
17
DDQ
31
3
1
, I/O
and BW
2
, BW
P1
3
-I/O
, BW
4
P4
are not applicable for the IDT71V3579.
4
(1)
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Linear / Interleaved Burst Order
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Address Status (Cache Controller)
Address Status (Processor)
Test Mode Select
Test Data Input
Test Clock
Test Data Output
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
1
Description
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
The IDT71V3577/79 are high-speed SRAMs organized as
The burst mode feature offers the highest level of performance to the
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
Supply
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
FEBRUARY 2009
IDT71V3577SA
IDT71V3579SA
Asynchronous
Asynchronous
Asynchronous
IDT71V3577S
IDT71V3579S
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
N/A
N/A
N/A
N/A
DC
DSC-5280/08
5280 tbl 01

Related parts for IDT71V3577S75BG

IDT71V3577S75BG Summary of contents

Page 1

... Features ◆ 128K x 36, 256K x 18 memory configurations ◆ ◆ ◆ ◆ ◆ Supports fast access times: Commercial: – 7.5ns up to 117MHz clock frequency Commercial and Industrial: – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode ◆ ...

Page 2

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Pin Definitions (1) Symbol Pin Function I Address Inputs ADSC Address Status I (Cache ...

Page 3

... Write Register Q D Enable Register CLK EN JTAG TDO (SA Version) 6.42 3 Commercial and Industrial Temperature Ranges INTERNAL Burst ADDRESS 128K x 36/ 17/18 256K x 18- BIT A0* Q0 MEMORY A1* ARRAY 36/18 Byte 1 Write Driver 9 Byte 2 Write Driver 9 Byte 3 Write Driver 9 Byte 4 Write Driver 9 DATA INPUT ...

Page 4

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with ...

Page 5

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 I/O ...

Page 6

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 256K x 18 100 ...

Page 7

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 119 BGA DDQ I/O 16 ...

Page 8

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 165 fBGA ( ...

Page 9

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ...

Page 10

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power ...

Page 11

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read Read Write all Bytes Write all Bytes (3) Write Byte 1 ...

Page 12

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Clock Parameter t Clock Cycle ...

Page 13

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Flow-Through Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 13 ...

Page 14

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Flow-Through Read and Write Cycles Commercial and Industrial Temperature Ranges 6.42 14 (1,2,3) , ...

Page 15

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 16

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges 6.42 16 (1,2,3) , ...

Page 17

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges , 6.42 17 (1,2,3) ...

Page 18

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA ...

Page 19

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ...

Page 20

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID ...

Page 21

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Ordering Information XXX Power Speed Device Type Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) 119 ...

Page 22

IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Datasheet Document History 7/23/99 9/17/99 Pg. 2 Pg. 3 Pg. 8 Pg. 18 Pg. 20 12/31/99 Pp ...

Related keywords