IDT71V65703S75PF IDT, Integrated Device Technology Inc, IDT71V65703S75PF Datasheet

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IDT71V65703S75PF

Manufacturer Part Number
IDT71V65703S75PF
Description
IC SRAM 9MBIT 75NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT71V65703S75PFG.pdf (26 pages)

Specifications of IDT71V65703S75PF

Format - Memory
RAM
Memory Type
SRAM - Synchronous ZBT
Memory Size
9M (256K x 36)
Speed
75ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71V65703S75PF

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(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBT
©2002 Integrated Device Technology, Inc.
R/
CLK
I/O
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
A
ADV/
ZZ
V
V
0
DD
SS
-A
0
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
Address and control signals are applied to the SRAM during one clock
1
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBT
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W W W W W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V (±5%) I/O Supply (V
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
1
-I/O
, CE
, V
,
18
DDQ
31
2
, I/O
TM
2
,
,
Feature - No dead cycles between write and read
P1
2
3
-I/O
,
P4
4
OE
OE
OE
OE
TM
BW
BW
BW
BW
, or Zero Bus Turnaround.
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Linear/Interleaved Burst Order
Sleep Mode
Data Input/Output
Core Power, I/O Power
Ground
Address Inputs
Advance Burst Address/Load New Address
DDQ
1
- BW
BW
BW
BW
BW
)
4
) control (May tie active)
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
1
cycle, and on the next clock cycle the associated data cycle occurs, be it
read or write.
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
to be suspended as long as necessary. All synchronous inputs are ignored when
CEN is high and the internal device registers will hold their previous values.
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
CMOS process and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
The IDT71V65703/5903 contain address, data-in and control signal
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903
There are three chip enable pins (CE
The IDT71V65703/5903 have an on-chip burst counter. In the burst
The IDT71V65703/5903 SRAMs utilize IDT’s latest high-performance
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
1
, CE
2
IDT71V65703
IDT71V65903
, CE
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
MARCH 2009
Static
Static
Static
N/A
2
) that allow the
DSC-5298/03
5298 tbl 01

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IDT71V65703S75PF Summary of contents

Page 1

... There are three chip enable pins (CE user to deselect the device when desired. If any one of these three is not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state one cycle after the chip is deselected or a write is initiated ...

Page 2

... R/ signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the curre nt cycle takes place one clock cycle later. Synchronous Clock Enable Input. When clock are ignored and outputs re main unchanged. The effect of outputs the low to high clock transition did no t occur ...

Page 3

... I/O, Burst Counter, and Flow-Through Outputs LBO Address A [0:17 R/W CEN ADV/LD BWx Clock Address D Q Control D Q Control Logic Clk Gate Data I/O [0:31], I/O P[1:4] 6.42 3 Commercial and Industrial Temperature Ranges 256K x 36 BIT MEMORY ARRAY DI DO Mux Sel , 5298 drw 01 ...

Page 4

... ____ ____ V + 0.3 V DDQ (1) ____ 0.8 V 5298 tbl 04 /2, once per cycle. CYC 6.42 4 Commercial and Industrial Temperature Ranges 512K x 18 BIT MEMORY ARRAY Address Control DI DO Mux Sel Gate Data I/O [0:15], I/O P[1:2] 5298 drw 01a , ...

Page 5

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs (1) Grade Temperature V SS Commercial 0°C to +70°C 0V Industrial -40°C to +85°C 0V NOTES the ...

Page 6

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs 100 ...

Page 7

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs DDQ I DDQ I ...

Page 8

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs ( I ...

Page 9

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs ( ADV ...

Page 10

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps ...

Page 11

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/ ADV n n n+3 X ...

Page 12

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/ ADV n NOTES High ...

Page 13

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/ ADV n n n+3 X ...

Page 14

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Cycle Address R/ ADV ...

Page 15

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Symbol Parameter |I | Input Leakage Current LI (1) Input Leakage Current | Output Leakage Current ...

Page 16

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t ...

Page 17

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 18

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 19

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 20

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs CEN Commercial and Industrial Temperature Ranges 6. ...

Page 21

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs CS Commercial and Industrial Temperature Ranges 6. ...

Page 22

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 22 ...

Page 23

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 23 ...

Page 24

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 6.42 24 ...

Page 25

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs OE OE DATA OUT NOTE read operation is assumed progress. XXXX S XX Device Power ...

Page 26

IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with 3.3V I/O, Burst Counter, and Flow-Through Outputs 12/31/99 04/20/00 Pg.5,6 Pg. 7 Pg. 21 05/23/00 Pg. 23 07/28/00 Pg. 5-8 Pg. 7,8 Pg. 23 11/04/00 Pg. 8 ...

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