IDT71V67903 Integrated Device Technology, IDT71V67903 Datasheet

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IDT71V67903

Manufacturer Part Number
IDT71V67903
Description
256k X 36, 512k X 18 3.3v Synchronous Srams 3.3v I/o, Burst Counter Flow-through Outputs, Single Cycle Deselect
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
IDT71V67903S75BG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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IDT71V67903S75BG8
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IDT71V67903S75BQ
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IDT71V67903S75BQ8
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IDT, Integrated Device Technology Inc
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10 000
Part Number:
IDT71V67903S75BQI
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IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. BW
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
©2002 Integrated Device Technology, Inc.
CS
CLK
I/O
A
ZZ
V
V
0
DD
SS
256K x 36, 512K x 18 memory configurations
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO
LBO
LBO input selects interleaved or linear burst mode
LBO
LBO
Self-timed write cycle with global write control (GW
enable (BWE
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O supply (V
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
The IDT71V67703/7903 are high-speed SRAMs organized as
-A
0
0
1
-I/O
,
, V
,
18
3
DDQ
and BW
31
1
, I/O
2
,
BWE
BWE
BWE
BWE), and byte writes (BW
P1
4
3
-I/O
are not applicable for the IDT71V67903.
,
P4
4
(1)
DDQ
)
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Address Status (Cache Controller)
Address Status (Processor)
BW
BW
BW
BWx)
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
GW
GW
GW
GW), byte write
1
data, address and control registers. There are no registers in the data
output path (flow-through architecture). Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
system designer, as the IDT71V67703/7903 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
The burst mode feature offers the highest level of performance to the
The IDT71V67703/7903 SRAMs utilize IDT’s latest high-performance
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
IDT71V67703
IDT71V67903
N/A
N/A
N/A
DC
DSC-5309/05
5309 tbl 01

Related parts for IDT71V67903

IDT71V67903 Summary of contents

Page 1

... Core Power, I/O Power DD DDQ V Ground SS NOTE and BW are not applicable for the IDT71V67903 ©2002 Integrated Device Technology, Inc. 256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect data, address and control registers. There are no registers in the data output path (flow-through architecture) ...

Page 2

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Pin Function I Address Inputs Address Status I (Cache Controller) Address Status I (Processor) Burst Address I Advance Byte Write Enable I Individual Byte Write Enables Chip Enable ...

Page 3

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect LBO AD V CLK AD SC ADSP A A 0– 17/ Powerdown O E 36/18 I/O –I I/O I/O P1– P4 Commercial and Industrial Temperature Ranges Burst ...

Page 4

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) V Terminal Voltage with TERM Respect to GND (5,6) V Terminal Voltage with TERM Respect to GND ...

Page 5

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect DDQ I DDQ DDQ V 21 ...

Page 6

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 100 DDQ I I DDQ ...

Page 7

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect DDQ I I DDQ DDQ DDQ DDQ DDQ I ...

Page 8

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect I/O I I/O I I/O I I I/O I I/O I I/O I I/O I I/O NC ...

Page 9

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL V Output High Voltage OH NOTE: 1. The LBO pin will be internally pulled to V ...

Page 10

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...

Page 11

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Operation Read Read Write all Bytes Write all Bytes (3) Write Byte 1 (3) Write Byte 2 (3) Write Byte 3 (3) Write Byte 4 NOTES Don’t Care. ...

Page 12

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Symbol Clock Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data CD t Clock High to Data Change ...

Page 13

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...

Page 14

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 15

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

Page 16

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...

Page 17

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 17 ...

Page 18

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect CLK ADDRESS CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. ...

Page 19

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...

Page 20

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...

Page 21

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...

Page 22

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect IDT XXX S X Device Power Speed Package Type XX X Process/ Temperature Rance Commercial (0°C to +70° C) Blank Industrial (-40° +85° 100-Pin Plastic Thin Quad Flatpack (TQFP) ...

Page 23

... IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Flow-Through Outputs, Single Cycle Deselect 12/31/99 Created Datasheet from 71V677 and 71V679 Datasheets For 2.5V I/O offering, see 71V67702 AND 71V67902 Datasheets. 04/26/00 Pg. 4 Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended Operating Temperature tables. Replace Pin U6 with TRST pin in BGA pin configuration ...

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