IDT72225 Integrated Device Technology, Inc., IDT72225 Datasheet

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IDT72225

Manufacturer Part Number
IDT72225
Description
CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
FEATURES:
• 256 x 18-bit organization array (IDT72205LB)
• 512 x 18-bit organization array (IDT72215LB)
• 1,024 x 18-bit organization array (IDT72225LB)
• 2,048 x 18-bit organization array (IDT72235LB)
• 4,096 x 18-bit organization array (IDT72245LB)
• 10 ns read/write cycle time
• Empty and Full flags signal FIFO status
• Easily expandable in depth and width
• Asynchronous or coincident read and write clocks
• Programmable Almost-Empty and Almost-Full flags with
• Half-Full flag capability
• Dual-Port zero fall-through time architecture
• Output enable puts output data bus in high-impedance
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP)
• Industrial temperature range (–40 C to +85 C) is available
DESCRIPTION:
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
FUNCTIONAL BLOCK DIAGRAM
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2000 Integrated Device Technology, Inc.
default settings
state
and plastic leaded chip carrier (PLCC)
Integrated Device Technology, Inc.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
(
)/
EXPANSION LOGIC
WRITE CONTROL
WRITE POINTER
RESET LOGIC
LOGIC
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
WCLK
CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18 and 4,096 x 18
OUTPUT REGISTER
1,024 x 18, 2,048 x 18
256 x 18, 512 x 18
INPUT REGISTER
RAM ARRAY
4,096 x 18
Q0-Q17
D0-D17
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
port is controlled by a free-running clock (WCLK), and an input
enable pin (
every clock when
by another clock pin (RCLK) and another enable pin (
read clock can be tied to the write clock for single clock
operation or the two clocks can run asynchronous of one
another for dual-clock operation. An Output Enable pin (
provided on the read port for three-state control of the output.
Full (
and Almost-Full (
flags is controlled by a simple state machine, and is initiated by
asserting the Load pin (
when the FIFO is used in a single device configuration.
technique. The XI and
In depth expansion configuration,
device and set to HIGH for all other devices in the Daisy Chain.
fabricated using IDT’s high-speed submicron CMOS technol-
ogy.
• •
• •
These FIFOs have 18-bit input and output ports. The input
The synchronous FIFOs have two fixed flags, Empty (
These devices are depth expandable using a Daisy-Chain
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
FF
), and two programmable flags, Almost-Empty (
WEN
PAF
). Data is read into the synchronous FIFO on
WEN
Commercial And Industrial Temperature Ranges
). The offset loading of the programmable
OFFSET REGISTER
XO
is asserted. The output port is controlled
READ CONTROL
READ POINTER
LD
RCLK
pins are used to expand the FIFOs.
). A Half-Full flag (
LOGIC
LOGIC
FLAG
FL
is grounded on the first
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
2766 drw 01
HF
) is available
MAY 2000
/(
REN
EF
DSC-2766/-
OE
). The
PAE
) and
)
1
1
) is
)

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IDT72225 Summary of contents

Page 1

... Integrated Device Technology, Inc. FEATURES: • 256 x 18-bit organization array (IDT72205LB) • 512 x 18-bit organization array (IDT72215LB) • 1,024 x 18-bit organization array (IDT72225LB) • 2,048 x 18-bit organization array (IDT72235LB) • 4,096 x 18-bit organization array (IDT72245LB) • read/write cycle time • Empty and Full flags signal FIFO status • ...

Page 2

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN CONFIGURATIONS V GND PIN ...

Page 3

... O When is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for IDT72225LB/72235LB/72245LB. PAF O When is LOW, the FIFO is almost full based on the offset programmed into the FIFO. ...

Page 4

... Input High Voltage 2.0 — Com'l/Ind'l Input Low Voltage — — Com'l/Ind'l Operating Temperature 0 — Commercial Operating Temperature –40 — Industrial 10 – + IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB (1) Commercial and Industrial t = 10, 15 CLK Typ. Max. — 1 — 10 — — — 0.4 — 60 — ...

Page 5

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Industrial Symbol Parameter ...

Page 6

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS ...

Page 7

... NOTES Empty Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127 Full Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127) EMPTY FLAG ( is HIGH, the WCLK input When the FIFO is empty, read operations. When The EF is updated on the LOW-to-HIGH transition of the REN read clock (RCLK) ...

Page 8

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes ...

Page 9

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WCLK SKEW1 RCLK NOTES the minimum time between a rising RCLK ...

Page 10

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK (first valid write ENS RCLK ...

Page 11

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t DS DATA WRITE ENS t ENH t t SKEW2 RCLK LOW Q ...

Page 12

... D = maximum FIFO Depth. Number of data words written into FIFO memory = 256 - for the IDT72205, 512 - for the IDT72215, 1,024 - for the IDT72225, 2,048 - for the IDT72235 and 4,096 - for the IDT72245. 2. 256 - m words in IDT72205, 512 - m words in IDT72215, 1,024 - m words in IDT72225, 2,048 - m words in IDT72235 and 4,096 - m words in IDT72245. WCLK ...

Page 13

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t ENS NOTE: 1. Write to Last Physical Location. RCLK t ENS NOTE: 1. Read from Last Physical Location. WCLK ...

Page 14

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72205LB/72215LB/72225LB/72235LB/72245LB may be used when the application requirements are for 256/ WRITE CLOCK (WCLK) ...

Page 15

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requir- ing more than 256/512/1,024/2,048/4,096 words of ...

Page 16

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available as standard product for ...

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