IDT72T36115 Integrated Device Technology, IDT72T36115 Datasheet

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IDT72T36115

Manufacturer Part Number
IDT72T36115
Description
128k X 36 Terasync Fifo, 2.5v - Best Value!
Manufacturer
Integrated Device Technology
Datasheet
1.IDT72T36115.pdf (57 pages)

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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
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FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Choose among the following memory organizations:
default to one of eight preselected offsets
Empty and Almost-Full flags
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
IDT72T36105 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T36115 ⎯ ⎯ ⎯ ⎯ ⎯
IDT72T36125 ⎯ ⎯ ⎯ ⎯ ⎯
WHSTL
RHSTL
ASYW
SHSTL
TRST
MRS
PRS
TMS
TDO
TCK
Vref
OW
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
BM
TDI
BE
IW
IP
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
65,536 x 36
131,072 x 36
262,144 x 36
(BOUNDARY SCAN)
WCS
CONFIGURATION
WRITE CONTROL
JTAG CONTROL
WRITE POINTER
CONTROL
CONTROL
RESET
HSTL I/0
LOGIC
LOGIC
WEN WCLK/WR
LOGIC
BUS
2.5 VOLT HIGH-SPEED TeraSync
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
OE
OUTPUT REGISTER
65,536 x 36, 131,072 x36
16,384 x 36, 32,768 x 36
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
Q
D
INPUT REGISTER
0
0
RAM ARRAY
-Q
262,144 x 36
-D
n
n
(x36, x18 or x9)
(x36, x18 or x9)
1
• • • • •
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• • • • •
• • • • •
• • • • •
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
Green parts are available, see ordering information
TM
FIFO 36-BIT CONFIGURATIONS
OFFSET REGISTER
READ POINTER
EREN
IDT72T36105, IDT72T36115, IDT72T36125
LOGIC
ERCLK
CONTROL
FLAG
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
LOGIC
READ
LD
SEN
RCS
REN
SCLK
RCLK/RD
5907 drw01
JANUARY 2007
RT
MARK
ASYR
FF/IR
PAF
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
EF/OR
DSC-5907/19

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IDT72T36115 Summary of contents

Page 1

... IDT72T3695 32,768 x 36 IDT72T36105 ⎯ ⎯ ⎯ ⎯ ⎯ 65,536 x 36 IDT72T36115 ⎯ ⎯ ⎯ ⎯ ⎯ 131,072 x 36 IDT72T36125 ⎯ ⎯ ⎯ ⎯ ⎯ 262,144 x 36 • • • • • 225 MHz Operation of Clocks • ...

Page 2

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PIN CONFIGURATION A1 ...

Page 3

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PIN CONFIGURATION (CONTINUED) ...

Page 4

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 DESCRIPTION: The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/ ...

Page 5

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 DESCRIPTION (CONTINUED) This ...

Page 6

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 WRITE CLOCK (WCLK/WR) ...

Page 7

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PIN DESCRIPTION Symbol ...

Page 8

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PIN DESCRIPTION (CONTINUED) ...

Page 9

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PIN DESCRIPTION (CONTINUED) ...

Page 10

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 ABSOLUTE MAXIMUM RATINGS ...

Page 11

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K ELECTRICAL CHARACTERISTICS ...

Page 12

... CC A Commercial Com’l & Ind’l IDT72T3645L4-4 IDT72T3645L5 IDT72T3655L4-4 IDT72T3655L5 IDT72T3665L4-4 IDT72T3665L5 IDT72T3675L4-4 IDT72T3675L5 IDT72T3685L4-4 IDT72T3685L5 IDT72T3695L4-4 IDT72T3695L5 IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10 IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10 IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10 Min. Max. Min. Max. — 225 — 200 0.6 3.4 0.6 3.6 4.44 — 5 — 2.0 — ...

Page 13

... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com’l & Ind’l Commercial IDT72T3645L5 IDT72T3645L6-7 IDT72T3655L5 IDT72T3655L6-7 IDT72T3665L5 IDT72T3665L6-7 IDT72T3675L5 IDT72T3675L6-7 IDT72T3685L5 IDT72T3685L6-7 IDT72T3695L5 IDT72T3695L6-7 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10 Min. Max. Min. Max. Min. — 83 — 66 — 0.6 10 0.6 12 0.6 12 — ...

Page 14

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 HSTL 1.5V AC ...

Page 15

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 OUTPUT ENABLE & ...

Page 16

... IDT72T3655, 4,096 writes for the IDT72T3665, 8,192 writes for the IDT72T3675, 16,384 writes for the IDT72T3685, 32,768 writes for the IDT72T3695, 65,536 writes for the IDT72T36105, 131,072 writes for the IDT72T36115 and 262,144 writes for the IDT72T36125, respectively. If the FIFO is full, the first read operation will cause HIGH. ...

Page 17

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 TABLE 2 — ...

Page 18

... IDT72T3675 IDT72T3665 n n+1 (n+2) to 2,049 (n+2) to 4,097 2,050 to (4,097-(m+1)) 4,098 to (8,193-(m+1)) to 4,096 (4,097-m) (8,193-m) 2,049 4,097 IDT72T36115 IDT72T36125 n n+1 (n+2) to 65,537 (n+2) to 131,073 65,538 to (131,073-(m+1)) 131,074 to (262,145-(m+1)) (131,073-m) to 131,072 (262,145-m) to 262,144 65,537 131,073 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FF ...

Page 19

... IDT72T3665 26 bits for the IDT72T3675 28 bits for the IDT72T3685 30 bits for the IDT72T3695 32 bits for the IDT72T36105 34 bits for the IDT72T36115 36 bits for the IDT72T36125 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) ...

Page 20

... IDT72T3665 13 bits for the IDT72T3675 14 bits for the IDT72T3685 15 bits for the IDT72T3695 16 bits for the IDT72T36105 17 bits for the IDT72T36115 18 bits for the IDT72T36125 Note: All unused bits of the LSB & MSB are don’t care Data Inputs/Outputs ...

Page 21

... IDT72T3655, 24 bits for the IDT72T3665, 26 bits for the IDT72T3675, 28 bits for the IDT72T3685, 30 bits for the IDT72T3695, 32 bits for the IDT72T36105, 34 bits for the IDT72T36115 and 36 bits for the IDT72T36125. See Figure 20, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode ...

Page 22

... LOW-to-HIGH transition of RCLK data on the outputs Qn are once again read from the Empty Offset Register LSB. For the IDT72T36115/72T36125, 6 enabled read cycles are required to read the offset registers, (3 per offset). Data on the outputs Qn are read from the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK. ...

Page 23

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 TABLE 5 — ...

Page 24

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 SIGNAL DESCRIPTION INPUTS: ...

Page 25

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 marked location. During ...

Page 26

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 into a high ...

Page 27

... IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125). See Figure 11, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information ...

Page 28

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 ECHO READ CLOCK ...

Page 29

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 BYTE ORDER ON ...

Page 30

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 BYTE ORDER ON ...

Page 31

... Figure 6. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS ( 2.5V IDT72T3645 IDT72T3655 Parameter IDT72T3665 IDT72T3675 IDT72T3685 IDT72T3695 JTAG Clock Input Period t IDT72T36105 JTAG Clock HIGH IDT72T36115 IDT72T36125 JTAG Clock Low Min. Max. Units JTAG Clock Rise Time - 20 ns JTAG Clock Fall Time JTAG Reset 10 ...

Page 32

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 JTAG INTERFACE Five ...

Page 33

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K Input ...

Page 34

... Part# Field IDT72T3645 IDT72T3655 IDT72T3665 IDT72T3675 IDT72T3685 IDT72T3695 IDT72T36105 IDT72T36115 IDT72T36125 31(MSB) Version (4 bits) 0X0 IDT72T3645/55/65/75/85/95/105/115/125 JTAG Device Identification Register JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: • ...

Page 35

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 HIGH-IMPEDANCE The optional ...

Page 36

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 MRS t RSS ...

Page 37

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 PRS t RSS ...

Page 38

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K WRITE WCLK ...

Page 39

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 RCLK t ENS ...

Page 40

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 41

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 42

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 43

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 44

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 45

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

Page 46

... for the IDT72T3645 for the IDT72T3655 for the IDT72T3665 for the IDT72T3675 for the IDT72T3685 for the IDT72T3695 for the IDT72T36105 for the IDT72T36115 and for the IDT72T36125. Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...

Page 47

... In IDT Standard mode 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665 and 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125. ...

Page 48

... In IDT Standard Mode: D=1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125. In FWFT Mode: D=1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125 ...

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... In FWFT mode maximum FIFO depth 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125. ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 COMMERCIAL AND INDUSTRIAL ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 WCLK t ENS ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 RCLK REN Qn ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K Write WCLK ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K CYC t ...

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IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync™ ™ ™ ™ ™ 36-BIT FIFO 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36 OPTIONAL CONFIGURATIONS WIDTH ...

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... IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125 with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...

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ORDERING INFORMATION IDT XXXXX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for 5ns speed is available as a standard device. All other speed grades are available by special order. 2. Green parts available. ...

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