IDT72V01 IDT [Integrated Device Technology], IDT72V01 Datasheet

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IDT72V01

Manufacturer Part Number
IDT72V01
Description
3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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FEATURES:
• 3.3V family uses 70% less power than the 5 Volt 7201/
• 512 x 9 organization (72V01)
• 1024 x 9 organization (72V02)
• 2048 x 9 organization (72V03)
• 4096 X 9 organization (72V04)
• Functionally compatible with 720x family
• 25 ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• Available in 32-pin PLCC and 28-pin SOIC Package (to
• Industrial temperature range (-40
DESCRIPTION:
memories that operate at a power supply voltage (Vcc)
between 3.0V and 3.6V. Their architecture, functional opera-
tion and pin assignments are identical to those of the IDT7201/
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
1996 Integrated Device Technology, Inc.
02/03/04 family
be determined)
able, tested to military electrical specifications
Integrated Device Technology, Inc.
The IDT72V01/72V02/72V03/72V04 are dual-port FIFO
W
XI
R
CONTROL
CONTROL
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
WRITE
READ
o
C to +85
3.3 VOLT CMOS
ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
EXPANSION
o
C) is avail-
LOGIC
LOGIC
FLAG
POINTER
WRITE
THREE-
STATE
BUFFERS
DATA OUTPUTS
5.08
DATA INPUTS
7202/7203/7204. These devices load and empty data on a
first-in/first-out basis. They use Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (
have a maximum data access time as fast as 25 ns.
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (
that allows for reset of the read pointer to its initial position
when
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.
IDT’s high-speed CMOS technology. It has been designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
(D –D
1024 x 9
2048 x 9
4096 x 9
ARRAY
(Q –Q
512x 9
RAM
0
The reads and writes are internally sequential through the
The devices utilize a 9-bit wide data array to allow for
The IDT72V01/72V02/72V03/72V04 is fabricated using
0
RT
8
8
EF
XO
)
FF
)
is pulsed low to allow for retransmission from the
/
HF
POINTER
READ
RESET
LOGIC
FL
RS
/
RT
W
) and Read (
2679 drw 01
R
DECEMBER 1996
) pins. The devices
IDT72V01
IDT72V02
IDT72V03
IDT72V04
RT
) capability
DSC-3033/6
1

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IDT72V01 Summary of contents

Page 1

... Industrial temperature range (-40 able, tested to military electrical specifications DESCRIPTION: The IDT72V01/72V02/72V03/72V04 are dual-port FIFO memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V. Their architecture, functional opera- tion and pin assignments are identical to those of the IDT7201/ FUNCTIONAL BLOCK DIAGRAM ...

Page 2

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 PIN CONFIGURATIONS GND 14 SMALL OUTLINE PACKAGE TO BE DETERMINED ABSOLUTE MAXIMUM RATINGS ...

Page 3

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 ELECTRICAL CHARACTERISTICS (Commercial 3.3 V 0.3V Symbol Parameter (1) I Input Leakage Current (Any Input) LI (2) I Output Leakage Current LO V Output Logic “1” Voltage Output Logic “0” Voltage I ...

Page 4

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 ELECTRICAL CHARACTERISTICS (Commercial 3.3V 0.3V + Symbol Parameter f Shift Frequency S t Read Cycle Time RC t Access Time A t Read Recovery Time RR (2) t Read Pulse Width RPW t Read Pulse Low to Data Bus at Low Z ...

Page 5

... The Single Device Mode is initiated by ). grounding the Expansion In ( The IDT72V01/72V02/72V03/72V04 can be made to re- transmit data when the Retransmit Enable control ( is pulsed low. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. ...

Page 6

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 low after 512/1024/2048/4096 writes to the IDT72V01/72V02/ 72V03/72V04 EMPTY FLAG ( ) EF The Empty Flag ( ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. ...

Page 7

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 LAST WRITE WFF FF LAST READ REF DATA OUT VALID RT W,R HF, EF, FF IGNORED FIRST READ ADDITIONAL WRITE t RFF Figure 4. Full Flag From Last Write to First Read ...

Page 8

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse W R HALF-FULL OR LESS HF WRITE TO LAST PHYSICAL LOCATION ...

Page 9

... FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT72V01/72V02/72V03/72V04 may be used when the application requirements are for 512/1024/2048/ 4096 words or less. IDT72V01/72V02/72V03/72V04 Single Device Configuration when the Expansion In ( control input is grounded (see Figure 12). Depth Expansion The IDT72V01/72V02/72V03/72V04 can easily be adapted to applications when the requirements are for greater than 512/1,024/2,048/4,096 words ...

Page 10

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 WRITE ( DATA IN (D) FULL FLAG ( RESET ( 18 DATA ( WRITE ( ) FF FULL FLAG ( ) RS RESET ( ) Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used in Width Expansion Mode TABLE I—RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode ...

Page 11

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 FULL RS Figure 14. Block Diagram of 3072 x 9 FIFO Memory (Depth Expansion) IDT 72V01/72V02 72V03/72V04 DEPTH , , EXPANSION BLOCK D – NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. ...

Page 12

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 SYSTEM A DATA DATA OUT DATA IN DATA OUT IDT B EF 72V01 B IDT 72V02 HF FF 7201A A 72V03 B 72V04 0 0-8 IDT 72V01 R W 72V02 ...

Page 13

... IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 ORDERING INFORMATION IDT XXXXX L XXX Device Type Power Speed X X Package Process/ Temperature Range Blank 72V01 72V02 72V03 72V04 5.08 COMMERCIAL TEMPERATURE RANGE Commercial ( Plastic Leaded Chip Carrier ...

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