IDT72V2103 IDT [Integrated Device Technology], IDT72V2103 Datasheet
IDT72V2103
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IDT72V2103 Summary of contents
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... FEATURES: • Choose among the following memory organizations: IDT72V2103 131,072 x 18/262,144 x 9 IDT72V2113 262,144 x 18/524,288 x 9 • • • • • Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs • • • • • ...
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... DESCRIPTION: The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improve- ments over previous SuperSync FIFOs, including the following: • ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 DESCRIPTION (CONTINUED) Each FIFO has a data input port (D ) and a data output port (Q n which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 DESCRIPTION (CONTINUED) not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use ...
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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V2103/72V2113 are fabricated using IDT’s high speed submi- cron CMOS technology. OW ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 PIN DESCRIPTION (TQFP & BGA PACKAGES) Symbol Name I/O BE During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES) Symbol Name I/O RM (1) Retransmit Timing I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select Mode normal latency mode ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 ABSOLUTE MAXIMUM RATINGS Symbol Rating (2) V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.15V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S (5) t Data Access Time ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter (4) f Cycle Frequency (Asynchronous mode (4) ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for t = 10ns ...
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... HF would toggle to LOW once the (D words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D the 65,538th word for the IDT72V2103 and 131,074th word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D the 131,074th word for the IDT72V2103 and 262,146th word for the IDT72V2113 ...
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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2103/ 72V2113 has internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE ≠ IDT72V2103 x18 Number of (n+1) to 65,536 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 1st Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 2nd Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 16 15 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 WCLK LD WEN REN SEN ...
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... IDT72V2103 and 38 bits for the IDT72V2113. For any other mode of operation (that includes x18 bus width on either the Input or Output), minus 2 bits from the values above. So, a total of 34 bits for the IDT72V2103 and 36 bits for the IDT72V2113. See Figure 15, Serial Loading of Programmable Flag Regis- ters, for the timing diagram for this mode ...
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... FIFO, between Reset (Master or Partial) and the time of Retransmit setup. If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 18-bit wide data ( data inputs for 9-bit wide data ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode ...
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... NARROW BUS FIFO after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. ...
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... In IDT Standard mode reads are performed after reset (MRS or PRS), HF will go LOW after (D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS OW RSS BE t RSS ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF NARROW BUS FIFO TM NARROW BUS FIFO ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 WRITE WCLK 1 t (1) SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 NARROW BUS FIFO TM NARROW BUS FIFO 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 NARROW BUS FIFO TM NARROW BUS FIFO 28 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ...
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... If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked. ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113 LOW 4 ...
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... If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked. ...
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... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113 LOW 4 ...
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... PAF offset . maximum FIFO depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. ...
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... PAF offset maximum FIFO Depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. ...
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... NOTES IDT Standard mode maximum FIFO depth. If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 RCLK REN FFA NOTE LOW and WEN = LOW. Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode) ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 Write WCLK 1 WEN SKEW t CYL Last Word W X NOTES LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 CYC t t CYH CYL Last Word in O/P Register t RPE t EFA EF NOTES LOW, WEN = LOW, and REN = LOW. ...
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... FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 29 demonstrates a width expansion using two IDT72V2103/ 72V2113 devices. If x18 Input or x18 Output bus Width is selected, D each device form a 36-bit wide input bus and Q a 36-bit wide output bus ...
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... Input or x18 Output bus Width is selected and 262,144 for the IDT72V2113. When both x9 Input and x9 Output bus Widths are selected, depths greater than 262,144 can be adapted for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 JTCKR t JTCKF t JTCKL TCK TDI/ TMS TDO t JRSR TRST (1) t JRST NOTE: 1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. ...
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... JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V2103/72V2113 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 Input = TMS NOTE: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V2103/72V2113, the Part Number field contains the following values: Device Part# Field ...
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... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order. DATASHEET DOCUMENT HISTORY 12/18/2000 pgs. 7, ...