IDT72V221 Integrated Device Technology, Inc., IDT72V221 Datasheet

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IDT72V221

Manufacturer Part Number
IDT72V221
Description
3.3 VOLT CMOS SyncFIFO?
Manufacturer
Integrated Device Technology, Inc.
Datasheet

Specifications of IDT72V221

Case
QFP

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are very high-speed, low-power First-In, First-Out (FIFO) memories with
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
256 x 9-bit organization IDT72V201
512 x 9-bit organization IDT72V211
1,024 x 9-bit organization IDT72V221
2,048 x 9-bit organization IDT72V231
4,096 x 9-bit organization IDT72V241
8,192 x 9-bit organization IDT72V251
10 ns read/write cycle time
5V input tolerant
Read and Write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set to
any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output Enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40 C to +85 C) is available
The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™
WRITE CONTROL
WCLK
WRITE POINTER
RESET LOGIC
WEN1
LOGIC
RS
WEN2
3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
OE
OUTPUT REGISTER
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
INPUT REGISTER
256 x 9, 512 x 9,
RAM ARRAY
D
Q
0
0
- D
- Q
8
8
1
clocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks and interprocessor
communication.
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every rising
clock edge when the Write Enable pins are asserted. The output port is
controlled by another clock pin (RCLK) and two Read Enable pins (REN1,
REN2). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (OE) is provided on the read port
for three-state control of the output.
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the Load pin (LD).
technology.
These FIFOs have 9-bit input and output ports. The input port is
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
These FIFOs are fabricated using IDT's high-speed submicron CMOS
OFFSET REGISTER
READ CONTROL
READ POINTER
RCLK
LOGIC
LOGIC
FLAG
REN1
REN2
LD
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
4092 drw 01
EF
PAE
PAF
FF
DSC-4092/2

Related parts for IDT72V221

IDT72V221 Summary of contents

Page 1

... IDT72V201 512 x 9-bit organization IDT72V211 1,024 x 9-bit organization IDT72V221 2,048 x 9-bit organization IDT72V231 4,096 x 9-bit organization IDT72V241 8,192 x 9-bit organization IDT72V251 10 ns read/write cycle time 5V input tolerant Read and Write clocks can be independent Dual-Ported zero fall-through time architecture ...

Page 2

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 INDEX PAF 3 ...

Page 3

... Input High Voltage 2.0 — Commercial/Industrial Input Low Voltage -0.5 — Commercial/Industrial Operating Temperature 0 — Commercial Operating Temperature -40 — Industrial = - +85 C) IDT72V201 IDT72V211 IDT72V221 IDT72V231 IDT72V241 IDT72V251 Commercial and Industrial ( 10, 15 CLK Typ. Max. — 1 — 10 — — — 0.4 — ...

Page 4

... D.U.T. GND to 3.0V 3ns 1.5V 1.5V See Figure 1 4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (2) Com'l & Ind'l Commercial IDT72V201L15 IDT72V201L20 IDT72V211L15 IDT72V211L20 IDT72V221L15 IDT72V221L20 IDT72V231L15 IDT72V231L20 IDT72V241L15 IDT72V241L20 IDT72V251L15 IDT72V251L20 Max. Min. Max. 66.7 — — 20 — 6 — 8 — ...

Page 5

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 DATA IN (D0 - D8) Data inputs for 9-bit wide data. RESET (RS) Reset is accomplished whenever ...

Page 6

... Full Offset (LSB) Default Value 007H (MSB) 0000 Figure 3. Offset Register Location and Default Values 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V221 - 1,024 x 9-BIT Empty Offset (LSB) Reg. Default Value 007H (MSB Full Offset (LSB) Reg. Default Value 007H 8 0 ...

Page 7

... If no reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 256 writes for the IDT72V201, 512 writes for the IDT72V211, 1,024 writes for the IDT72V221, 2,048 writes for the IDT72V231, 4,096 writes for the IDT72V241 and 8,192 writes for the IDT72V251. ...

Page 8

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 REN1, REN2 WEN1 (1) WEN2/LD EF, PAE FF, PAF NOTES: 1. ...

Page 9

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 RCLK t t ENS ENH REN1, REN2 OLZ OE WCLK ...

Page 10

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 WRITE WCLK t SKEW1 WEN1 WEN2 (If Applicable) RCLK t ...

Page 11

... NOTES PAF offset. 2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m words for IDT72V251. is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and 3 ...

Page 12

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN1 ...

Page 13

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 SINGLE DEVICE CONFIGURATION A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be used when the application requirements are for 256/512/1,024/2,048/4,096/ 8,192 ...

Page 14

IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns is available as a standard device. All other speed grades are available by special order. 01/11/2002 pg. 3. 02/01/2002 pg. 3. CORPORATE HEADQUARTERS ...

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