IDT72V245 Integrated Device Technology, Inc., IDT72V245 Datasheet
IDT72V245
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IDT72V245 Summary of contents
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... • • • • • 1,024 x 18-bit organization array (IDT72V225) • • • • • 2,048 x 18-bit organization array (IDT72V235) • • • • • 4,096 x 18-bit organization array (IDT72V245) • • • • • read/write cycle time • • • • • 5V input tolerant • ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DESCRIPTION (CONTINUED) The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN DESCRIPTION Symbol Name D0–D17 Data Inputs I RS Reset I WCLK Write Clock I WEN Write Enable I RCLK ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Parameter Min. Typ. 3.0 3 2.0 — -0.5 — 0 — ⎯ -40 IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V245 Commercial & Industrial ( 10, 15 CLK Typ. Max. — 1 — 10 — — — 0.4 — 30 — capacitive load (in pF FEBRUARY 22, 2006 Max. ...
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... Includes jig and scope capacitances. See Figure 1 5 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Com'l & Ind'l (1) Commercial IDT72V205L15 IDT72V205L20 IDT72V215L15 IDT72V215L20 IDT72V225L15 IDT72V225L20 IDT72V235L15 IDT72V235L20 IDT72V245L15 IDT72V245L20 Min. Max. Min. Max. — 66.7 — — 20 — 6 — 8 — ...
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... IDT72V205, (512-m) writes for the IDT72V215, (1,024-m) writes for the IDT72V225, (2,048-m) writes for the IDT72V235 and (4,096–m) writes for the IDT72V245. The offset “m” is the full offset value. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If there ...
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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FF PAF IDT72V245 ( 2,048 H H (2) (2) 2,049 to (4,096-(m+1 (4,096-m) to 4,095 H L 4,096 PAF HF PAE OR IDT72V245 ( 2,049 L H (2) (2) 2,050 to (4,097-(m+1 (4,097-m) to 4,096 L L 4,097 H L FEBRUARY 22, 2006 HF PAE ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET FL RXI WXI EF/ Single register-buffered Empty Flag ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS: RESET (RS) ...
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... In FWFT mode reads are performed, PAF will go LOW after 257-m for the IDT72V205, 513-m for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. The default values for m are noted in Table 1 and 2. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK) ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 REN, WEN, LD (1) FL, RXI, WXI (2) RCLK, WCLK FF/IR EF/OR PAF, WXO/ HF, RXO PAE Q - ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 RCLK t t ENS ENH REN OLZ OE WCLK WEN NOTES: is ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK (1) t SKEW1 WEN RCLK t t ENS ENH REN OE ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN ...
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... D = maximum FIFO Depth. In IDT Standard Mode 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK WXO t ENS WEN NOTE: 1. Write to Last Physical Location. RCLK RXO t ENS REN NOTE: 1. Read ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 COMMERCIAL AND INDUSTRIAL 17 TEMPERATURE RANGES FEBRUARY 22, 2006 ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES FEBRUARY 22, 2006 ...
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... D = maximum FIFO Depth. In IDT Standard Mode 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 RCLK t t ENH ENS REN t REF OLZ t OE ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72V205/72V215/72V225/72V235/72V245 may be used when the application requirements are for 256/512/1,024/2,048/4,096 words or ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more ...
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IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION (FWFT MODE) In FWFT mode, the FIFOs can be connected in series (the data outputs of one ...
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ORDERING INFORMATION XXXXX X XX IDT Device Type Power Speed NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are ...