IDT72V255 Integrated Device Technology, Inc., IDT72V255 Datasheet

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... Green parts available, see ordering information DESCRIPTION: The IDT72V255LA/72V265LA are functionally compatible versions of the IDT72255/72265 designed to run off a 3.3V supply for very low power consumption. The IDT72V255LA/72V265LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 DESCRIPTION (CONTINUED) • • • • • The period required by the retransmit operation is now fixed and short. • • • • • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short ...

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... Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V255LA/72V265LA are fabricated using IDT’s high speed submicron CMOS technology. PARTIAL RESET (PRS) ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PIN DESCRIPTION Symbol Name D –D Data Inputs 0 17 MRS Master Reset PRS Partial Reset RT Retransmit FWFT/SI First Word Fall Through/Serial In WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH t Clock Low Time ...

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... See section on Programmable Flag Offset Loading. When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations reads are performed after a reset, FF will go LOW after D writes to the FIFO 8,192 writes for the IDT72V255LA and 16,384 for the IDT72V265LA, respectively. COMMERCIAL AND INDUSTRIAL If the FIFO is full, the first read operation will cause HIGH ...

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... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V255LA/72V265LA has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values can be programmed into the FIFO in one of two ways; serial or parallel loading method ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 IDT72V255LA  8,192 BIT 17 12 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, 3FFH HIGH at Master Reset 17 12 FULL OFFSET REGISTER DEFAULT VALUE 07FH LOW at Master Reset, ...

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... D –2 words should have been written into the FIFO between Reset (Master or Partial) and the time of Retransmit setup 8,192 for the IDT72V255LA and D = 16,384 for the IDT72V265LA. In FWFT mode 8,193 for the IDT72V255LA and D = 16,385 for the IDT72V265LA. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 SIGNAL DESCRIPTION INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array ...

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... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO (D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA) See Figure 9, Write Timing (FWFT Mode), for the relevant timing information ...

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... The default setting for this value is stated in the footnote of Table 1. In FWFT mode, the PAF will go LOW after (8,193-m) writes for the IDT72V255LA and (16,385-m) writes for the IDT72V265LA, where m is the full offset value. The default setting for this value is stated in the footnote of Table 2. ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 MRS REN WEN t FWFT FWFT/ SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSS t If FWFT = HIGH HIGH RSF If FWFT = LOW LOW t If FWFT = LOW HIGH RSF ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 PRS REN WEN RT SEN EF/OR FF/IR PAE PAF RSS t RSS t RSS t RSS t RSF If FWFT = LOW HIGH t RSF If FWFT = HIGH LOW t RSF t RSF t RSF Figure 6. Partial Reset Timing 16 COMMERCIAL AND INDUSTRIAL ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH REN DATA IN OUTPUT REGISTER NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t 1 ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES OCTOBER 17, 2005 ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES OCTOBER 17, 2005 ...

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... FIFO after Master Reset more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure 8,192 for IDT72V255LA and 16,384 for IDT72V265LA goes HIGH RCLK cycle + t REF ...

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... OR goes LOW RCLK cycles + t REF WCLK t t ENS SEN t t LDS BIT 0 SI NOTE for the IDT72V255LA and for the IDT72V265LA. Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes x+1 t SKEW4 ENH t REF PAF ...

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... PAF offset maximum FIFO depth. In IDT Standard mode 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA. In FWFT mode 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA. is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t 3 ...

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... REN NOTES: 1. For IDT Standard mode maximum FIFO depth 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA. 2. For FWFT mode maximum FIFO depth 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA. Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes) ...

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... OR of every FIFO, and separately ORing IR of every FIFO. Figure 23 demonstrates a width expansion using two IDT72V255LA/ 72V265LA devices D17 from each device form a 36-bit wide input bus and Q0-Q17 from each device form a 36-bit wide output bus. Any word width can be attained by adding additional IDT72V255LA/72V265LA devices ...

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... FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 24 shows a depth expansion using two IDT72V255LA/ 72V265LA devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next (" ...

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... IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18, 16,384 x 18 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. For specific speeds and packages contact your sales office. ...

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... DIFFERENCES BETWEEN THE IDT72V255LA/72V265LA AND IDT72V255L/72V265L IDT has improved the performance of the IDT72V255/72V265 SuperSync™ FIFOs. The new versions are designated by the “LA” mark. The LA part is pin-for-pin compatible with the original “L” version. Some difference exist between the two versions. The following table details these differences. ...