IDT72V36106 IDT [Integrated Device Technology], IDT72V36106 Datasheet

IDT72V36106

Manufacturer Part Number

IDT72V36106

Description

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

Manufacturer

IDT [Integrated Device Technology]

Datasheet

1.IDT72V36106.pdf (39 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

IDT72V36106L10PF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT72V36106L10PF8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT72V36106L15PF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT72V36106L15PF8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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FEATURES

• • • • •

COMMERICAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.



EFA/ORA

FS1/SEN

RTM

RT1

RT2

FFA/IRA

36-bit port and two unidirectional 18-bit ports (Port C receives

and Port B transmits)

Ports B and C

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRC flag functions)

five default offsets (8, 16, 64, 256 and 1024)

Memory storage capacity:

Clock frequencies up to 100 MHz (6.5ns access time)

Two independent FIFOs buffer data between one bidirectional

18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag

Programmable Almost-Empty and Almost-Full flags; each has

FS0/SD

PRS1

LOOP

MRS1

MBF2

CLKA

W/RA

MBA

CSA

ENA

AFA

AEA

FS2

-A

FIFO1 and

FIFO2

Retransmit

Logic

IDT72V3686 – 16,384 x 36 x 2

IDT72V3696 – 32,768 x 36 x 2

IDT72V36106 – 65,536 x 36 x 2

Control

FIFO1,

Mail1

Reset

Logic

Port-A

Logic

3.3 VOLT CMOS TRIPLE BUS SyncFIFO

16,384 x 36 x 2

32,768 x 36 x 2

65,536 x 36 x 2

FIFO1

FIFO2

Programmable Flag

Offset Registers

Pointer

Write

Read

16,384 x 36

32,768 x 36

65,536 x 36

16,384 x 36

32,768 x 36

65,536 x 36

Status Flag

RAM ARRAY

Mail 1

Mail 2

Logic

Pointer

Timing

Read

Mode

Write

• • • • •

Serial or parallel programming of partial flags

Big- or Little-Endian format for word and byte bus sizes

Loopback mode on Port A

Retransmit Capability

Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

Mailbox bypass registers for each FIFO

Free-running CLKA, CLKB and CLKC may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

Auto power down minimizes power dissipation

Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

Pin compatible to the lower density parts, IDT72V3626/72V3636/

72V3646/72V3656/72V3666/72V3676

Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available

WITH BUS-MATCHING

NOVEMBER 2003

(B and C)

Common

Control

Port-B

Logic

Port-C

FIFO2,

Mail2

Reset

Logic

Port

Logic

IDT72V36106

IDT72V3686

IDT72V3696

4676 drw01

MBF1

CLKB

RENB

CSB

MBB

SIZEB

EFB/ORB

AEB

FWFT

FFC/IRC

AFC

MRS2

PRS2

CLKC

WENC

MBC

SIZEC

DSC-4676/4

-B

-C

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