IDT72V90823 Integrated Device Technology, IDT72V90823 Datasheet

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... DESCRIPTION: The IDT72V90823 is a non-blocking digital switch that has a capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. Some of the main features are: programmable stream and channel control, Processor Mode, input offset delay and high-impedance output control ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 PIN CONFIGURATIONS INDEX RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE/HCLK GND CLK VCC NOTES: 1. DNC - Do Not Connect 2 ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 PIN CONFIGURATIONS (CONTINUED) 76 DNC 77 DNC 78 RX0 RX1 79 RX2 80 RX3 81 RX4 82 RX5 83 RX6 84 RX7 85 RX8 86 RX9 87 RX10 88 RX11 89 RX12 90 RX13 91 RX14 92 RX15 93 F0i 94 FE/HCLK 95 GND 96 CLK 97 VCC 98 DNC 99 DNC 100 INDEX RX0 81 RX1 82 RX2 ...

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... This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V90823 is in the normal functional mode. Connect to GND for normal operation. This pin must be low for the IDT72V90823 to function normally and to comply with IEEE 1114 (JTAG) boundary scan requirements. ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 PIN DESCRIPTION (CONTINUED) SYMBOL NAME I/O IM (1) CPU Interface Mode I AD0-7 (1) Address/Data Bus I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins D8-15 Data Bus 8-15 I/O These pins are the eight most significant data bits of the microprocessor port. ...

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... The serial input streams of the IDT72V90823 can have a bit rate of 2.048, 4.096 or 8.192 Mb/s and are arranged in 125µs wide frames, which contain 32 128 channels respectively. The data rates on input and output streams are identical ...

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... If the input channel n is Capacity switched to output channel n+3, n+4,..., the new output data will appear in the 512 x 512 same frame. Table 2 shows the possible delays for the IDT72V90823 in the 1,024 x 1,024 variable delay mode. 2,048 x 2,048 ...

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... Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V90823, the minimum throughput delay achievable in the constant delay mode will be one frame. For example Mb/s mode, when input time- slot 31 is switched to output time-slot 0 ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 Control Register The Control Register is only accessed when A7-A0 are all zeroed. When A7 = 128 bytes are randomly accessa- ble via A0-A6 at any one instant. Of which stream these bytes (channels) are accessed is determined by the state - ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 2 — VARIABLE THROUGHPUT DELAY VALUE Input Rate 2.048 Mb/s 32 – (n-m) time-slots 4.096 Mb/s 64 – (n-m) time-slots 8.192 Mb/s 128 – (n-m) time-slots TABLE 3 — CONSTANT THROUGHPUT DELAY VALUE Input Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s TABLE 4 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 5 — OUTPUT HIGH IMPEDANCE CONTROL OE bit in Connection Memory TABLE 6 — CONTROL REGISTER (CR) BITS Read/Write Address Reset Value: 0000 . Bit Name 15-6 Unused Must be zero for normal operation. ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 8 — INTERFACE MODE SELECTION (IMS) REGISTER BITS Read/Write Address Reset Value: 0000 . Bit Name 15-10 Unused 9-5 BPD4-0 (Block Programming Data) 4 BPE (Begin Block Programming Enable) 3 OSB (Output Stand By) ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 10 — FRAME ALIGNMENT REGISTER (FAR) BITS Read/Write Address Reset Value: 0000 . CFE FD11 FD10 Bit Name 15-13 Unused 12 CFE (Complete Frame Evaluation) 11 FD11 (Frame Delay Bit 11) 10-0 FD10-0 (Frame Delay Bits)  ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 11 — FRAME INPUT OFFSET REGISTER (FOR) BITS Read/Write Address: 03 for FOR0 register for FOR1 register for FOR2 register for FOR3 register, H Reset Value: 0000 for all FOR registers ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 12 — OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS (FD11, FD2-0) Input Stream Offset No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2 ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 13 — CONNECTION MEMORY BITS V/C LPBK PC CCO OE Bit Name 15 LPBK (Per Channel Loopback) V/C 14 (Variable/Constant Throughput Delay (Processor Channel) 12 CCO (Control Channel Output (Output Enable) (1) 10-8,7 SAB3-0 (Source Stream Address Bits) ...

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... As specified in IEEE 1149.1, the IDT72V90823 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V90823 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 TABLE 15 — BOUNDARY SCAN REGISTER BITS Boundary Scan Bit 0 to bit 117 Device Pin Three-State Control Scan Cell TX7 0 TX6 2 TX5 4 TX4 6 TX3 8 TX2 10 TX1 12 TX0 14 ODE CCO 17 DTA D15 20 D14 23 D13 26 D12 ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC Vi Voltage on Digital Inputs (3.3V) GND -0.3 Vi Voltage on Digital Inputs (5.0V) GND -0.3 I Current at Digital Outputs O T Storage Temperature S P Package Power Dissapation D NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK Symbol Characteristics ® t Frame Pulse Width (ST-BUS FPW t Frame Pulse Setup time before CLK falling (ST-BUS FPS t Frame Pulse Hold Time from CLK falling (ST-BUS FPH CLK Period  ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 t FPW F0i t FPS CLK TX (1) Bit 0, Last Ch RX (1) Bit 0, Last Ch NOTE: 1. 2.048 Mb/s mode, last channel = ch 31, 4.096 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127. Figure 7. ST-BUS ® Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0. ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 t F0i HCLK 4.096 MHz CLK 16.384 MHz TX Bit 1, Ch 127 Bit 1, Ch 127 Bit 0, Ch 127 RX NOTE: 1. High Impedance is measured by pulling to the appropriate rail with R Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1 CLK  ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL) Symbol Parameter t ALE Pulse Width ALW t Address Setup from ALE falling ADS t Address Hold from ALE falling ADH RD Active after ALE falling t ALRD Data Setup from DTA LOW on Read ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA) Symbol Parameter t ALE Pulse Width ASW t Address Setup from AS falling ADS t Address Hold from AS falling ADH Data Setup from DTA LOW on Read t DDR CS Hold after DS falling t CSH ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE Symbol Parameter t CS Setup from DS falling CSS t R/W Setup from DS falling RWS t Address Setup from DS falling ADS t CS Hold after DS rising CSH t R/W Hold after DS Rising RWH t Address Hold after DS Rising ...

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... IDT72V90823 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048 CLK GCI  CLK ST-BUS t DSS DS t CSS CS t RWS R/W t ADS A0-A7 AD0-AD7/ D8-D15 DTA Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing t DSS t DSPW t t CSS CSH RWH RWS ADH ADS VALID READ ...

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ORDERING INFORMATION IDT XXXXXX XX Device Type Package DATASHEET DOCUMENT HISTORY 5/19/2000 pgs. 1,3,18 and 25. 7/27/2000 pgs and 25. 8/14/2000 pg. 6. 9/14/2000 pgs 12, 13 and 18. 1/02/2001 pgs. ...