IR22141 International Rectifier, IR22141 Datasheet
IR22141
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IR22141 Summary of contents
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... The IR2214SS/IR22141SS driver features full short circuit protection by means of the power transistor desaturation detection. The IR2214SS/IR22141SS manages all the half-bridge faults by turning off smoothly the desaturated tran- sistor through the dedicated soft shut down pin, therefore preventing over-volt- ages and reducing EM emissions ...
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... IR2214/IR22141(SS) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to V SS, dissipation ratings are measured under board mounted and still air conditions. Symbol V High side offset voltage ...
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... Logic "0" input bias current IN- R FAULT/SD open drain resistance ON,FLT R SY_FLT open drain resistance ON,SY HIN/LIN/ FLTCLR Figure 2: HIN, LIN and FLTCLR diagram www.irf.com IR2214/IR22141(SS) ADVANCE DATA ÷ 1200 V and unless otherwise specified Min Typ Max Units Test Conditions 9.3 10.2 11.4 8 ...
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... IR2214/IR22141(SS) FAULT/SD SY_FLT V SS Figure 3: FAULT/SD and SY_FLT diagram Pin: DSL, DSH The active bias is present only in IR22141. V respectively for DSL and DSH. Symbol Definition V High desat input threshold voltage DESAT+ V Low desat input threshold voltage DESAT- V Desat input voltage hysteresis ...
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... Soft Shutdown on resistance (Note 1) ON,SSD I Output low short circuit pulsed current O- Note 1: SSD operation only. on/off internal signal desat internal signal Figure 6: HON, LON, SSDH and SSDL diagram www.irf.com IR2214/IR22141(SS) ADVANCE DATA – –V B HOP or cc LOP 200ns Figure 5: HOP and LOP diagram V ...
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... IR2214/IR22141(SS) AC Electrical Characteristics 15V and Symbol Definition ton Turn on propagation delay toff Turn off propagation delay tr Turn on rise time (C LOAD tf Turn off fall time (C LOAD ton1 Turn on first stage duration time t DSH to HO soft shutdown propagation delay at HO ...
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... HIN 50% LIN (HOP=HON) LO (LOP=LON) 10% Figure 7: Switching Time Waveforms www.irf.com IR2214/IR22141(SS) ADVANCE DATA 50 out 90% Ton1 Io1+ Io2+ Figure 8: Output Source Current 3. off f 90% 10% 7 ...
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... IR2214/IR22141(SS) HIN/LIN DSH/DSL SSD Driver Enable HO/LO Figure 9: Soft Shutdown Timing Waveform 8 ADVANCE DATA DESAT+ t DESAT 3.3V V DESAT www.irf.com ...
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... DSL SY_FLT 50% t SY_FLT,DESAT1 FAULT/SD FLTCLR 90% SoftShutdown 50% 50% HON 10 DESAT1 on LON LIN 50% HIN HO (HOP=HON) LO (LOP=LON) 50% www.irf.com IR2214/IR22141(SS) ADVANCE DATA 50% 8V 50% 50 SY_FLT,DESAT2 SY_FLT,DESAT3 90% SoftShutdown t DESAT2 90% 50% SoftShutdown 10 DESAT3 t on Figure 10: Desat Timing 50% 50% DTH MDT=DTH-DTL ...
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... IR2214/IR22141(SS) Lead Assignments 24-Lead SSOP – IR2214SS Lead Definitions Symbol VCC Low side gate driver supply VSS Logic Ground HIN Logic input for high side gate driver outputs (HOP/HON) LIN Logic input for low side gate driver outputs (LOP/LON) Dual function (in/out) active low pin. Refer to figures 17, 18 and 15 output, indicates fault FAULT/SD condition ...
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... PREVENTION (DT) Deadtime UV_VCC DETECT UV_VCC SSD HOLD FAULT LOGIC SY_FLT managemend FAULT SD FAULT/SD (See figure 14) FLT_CLR VSS www.irf.com IR2214/IR22141(SS) ADVANCE DATA on/off (HS) on/off LOCAL DESAT OUTPUT LEVEL PROTECTION SHUTDOWN SHIFTERS LOGIC on/off (LS) desat SOFT SHUTDOWN UV_VBS DETECT DesatHS LOCAL DESAT PROTECTION ...
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... IR2214/IR22141(SS) State Diagram FAULT DESAT EVENT Soft ShutDown Stable State FAULT HO=LO=0 (Normal operation) HO/LO=1 (Normal operation) UNDERVOLTAGE V CC SHUTDOWN (SD) UNDERVOLTAGE V BS FREEZE NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE2: Exiting from UNDERVOLTAGE V happens ...
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... Under Voltage X X NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required. In order to avoid FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active. www.irf.com IR2214/IR22141(SS) ADVANCE DATA IR2214 Logic Table SSDH/SSDL 0 HiZ HiZ HiZ ...
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... IR2214/IR22141(SS) FEATURES DESCRIPTION 1. Start-up sequence At power supply start- recommended to keep FLT_CLR pin active until supply voltages are properly established. This prevents spurious diagnostic signals being generated. All protection functions are operating independently from FLT_CLR status and output driver status reflects the input commands ...
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... BL Blanking tss One Shot DesatHS/ filter Figure 13: high and low side output stage www.irf.com IR2214/IR22141(SS) ADVANCE DATA of an external high voltage diode. High current in does not the IGBT may cause the transistor to desaturate increase. CE undervoltage Once in desaturation, the current in power ...
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... V /I DSH/L CC DS- IR2214 dedicated circuit (see the active- bias section for the IR22141). When V creases, the voltage at DSH/L pin increases too. Being internally biased to the local supply, DSH/L voltage is automatically clamped. When DSH/L exceeds the V threshold the com- DESAT+ parator triggers (see figure 13) ...
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... When SYS_FLT is active all the drivers hold their output state regardless the input signals ( they receive from the IN IN controller (freeze state). This feature is particularly important in phase- www.irf.com IR2214/IR22141(SS) ADVANCE DATA VB VCC HOP LIN HOP HON HIN HON ...
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... ADVANCE DATA An Active Bias structure is available only for IR22141 version for DSH/L pin. The DSH/L pins present an active pull-up respectively to VB/VCC, and a pull-down respectively to VS/COM. The dedicated biasing circuit reduces the impedance on the DSH/L pin when the voltage exceeds the V threshold (see figure 16) ...
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... DSL SY_FLT FAULT/SD FLT_CLR HO(HOP/HON) LO(LOP/LON) Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output www.irf.com IR2214/IR22141(SS) ADVANCE DATA 7. Timing and logic state diagrams O- description The following figures show the input/output logic diagram. Figure 17 shows the SY_FLT and FAULT/SD signals as output, whereas figure 18 shows them as input ...
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... IR2214/IR22141(SS) HIN LIN SY_FLT FAULT/SD FLT_CLR HO (HOP/HON) LO (LOP/LON) Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input Referred to timing diagram of figure 17: A. When the input signals are on together the outputs go off (anti-shoot through). B. The HO signal is on and the high side IGBT desaturates, the HO turn off softly while the SY_FLT stays low ...
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... Bootstrap capacitor sizing To size the bootstrap capacitor, the first step is to establish the minimum voltage drop ( V that we have to guarantee when the high side IGBT is on. www.irf.com IR2214/IR22141(SS) ADVANCE DATA the minimum gate emitter voltage we GEmin want to maintain, the voltage drop must be: ...
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... IR2214/IR22141(SS) The minimum size of bootstrap capacitor is: Q TOT C BOOT min example follows: a) using a 25A @ 125C IGBT (IRGP30B120KD): = 800 µA (See Static Electrical Charact.); I QBS = 50 µA (See Static Electrical Charact.); nC 160 nC (Datasheet IRGP30B120KD 100 nA (Datasheet IRGP30B120KD); I LK_GE = 100 µ ...
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... V supply CC www.irf.com IR2214/IR22141(SS) ADVANCE DATA Gate resistances The switching speed of the output transistor can be controlled by properly size the resistors con- trolling the turn-on and turn-off gate current. The ...
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... IR2214/IR22141(SS) Sizing the turn-on gate resistor Switching-time For the matters of the calculation included here- after, the switching time t is defined as the time sw spent to reach the end of the plateau voltage (a total Q +Q has been provided to the IGBT gate obtain the desired switching time the gate ...
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... IGBT Qge Qgc IRGP30B120K(D) 19nC 82nC IRG4PH30K(D) 10nc 20nC Table 3: R sizing Goff IGBT Vth(min) IRGP30B120K(D) 4 IRG4PH30K(D) 3 www.irf.com IR2214/IR22141(SS) ADVANCE DATA Translated into equations Goff th Goff Rearranging the equation yields: flowing in R Goff R Goff When R Goff (I Vcc example, table 3 reports R ...
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... IR2214/IR22141(SS) PCB LAYOUT TIPS : Distance from voltage The IR2214 pin out maximizes the distance be- tween floating (from DC- to DC+) and low voltage pins. It’s strongly recommended to place com- ponents tied to floating voltage in the high volt- age side of device ( side) while the other ...
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... Figure 24: layout example: top (a), bottom (b) Referred to figure 24: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3 www.irf.com IR2214/IR22141(SS) ADVANCE DATA D2 DC Phase and ground plane (c) layer ...
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... IR2214/IR22141(SS) Case outline IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 28 ADVANCE DATA 24-Lead SSOP Data and specifications subject to change without notice. 12/17/2003 01 6076 01 01 5537 01 MO-150AH www.irf.com ...