IR3087M International Rectifier, IR3087M Datasheet

IC XPHASE W/OVP/TM CTRL 20-MLPQ

IR3087M

Manufacturer Part Number
IR3087M
Description
IC XPHASE W/OVP/TM CTRL 20-MLPQ
Manufacturer
International Rectifier
Series
XPhase™r
Datasheet

Specifications of IR3087M

Applications
Processor
Current - Supply
10mA
Voltage - Supply
8.4 V ~ 21 V
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-MLPQ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*IR3087M
DESCRIPTION
FEATURES
APPLICATION CIRCUIT
XPHASE
Page 1 of 35
The IR3087 Phase IC combined with an IR XPhase
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The XPhase
expensive, and easier to design while providing higher efficiency than conventional approaches.
The IR3087 with Opti-Phase
light load conditions. Both gate drivers will drive low at a programmable output current threshold. This
effectively disconnects the phase from the load eliminating power losses due to switching and circulating
currents.
5 Wire Analog Bus
From Control IC
2.5A Average Gate Drive Current
Loss-Less Inductor Current Sense
Internal Inductor DCR Temperature Compensation
Programmable Phase Delay
Programmable Feed-Forward Voltage Mode PWM Ramp
Sub 100ns Minimum Pulse Width supports 1MHz per-phase operation
Current Sense Amplifier drives a single wire Average Current Share Bus
Current Share Amplifier reduces PWM Ramp slope to ensure sharing between phases
Body Braking
output voltage at converter turn-off
Opti-Phase
OVP comparator with 150ns response
Programmable Phase Over-Temperature Detection
Small thermally enhanced 20L MLPQ package
TM
PHASE IC WITH OPTI-PHASE
TM
TM
reduces the number of phases for improved light to medium load efficiency
VGATE
VRHOT
ISHARE
disables Synchronous MOSFET for improved transient response and prevents negative
DAC
BIAS
RAMP
12V
EA
TM
is intended for applications demanding increased efficiency under medium to
ROP1
RBIASIN
1
2
3
4
5
CSCOMP
RMPIN+
RMPIN-
HOTSET
VRHOT
ISHARE
20k
ROP2
TM
architecture results in a power supply that is smaller, less
IR3087
PHASE
IC
TM
Control IC provides a full featured and flexible way to
TM
RCS-
CCS-
, OVP, AND OVERTEMP DETECT
CVCC
GATEH
GATEL
VCCH
PGND
VCCL
RVCC
RPWMRMP
15
14
13
12
11
DBST
CVCCL
CCS+
RCS+
CBST
L
CO
DATA SHEET
CIN
1
/31/05
IR3087
VO

Related parts for IR3087M

IR3087M Summary of contents

Page 1

TM XPHASE PHASE IC WITH OPTI-PHASE DESCRIPTION The IR3087 Phase IC combined with an IR XPhase implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of ...

Page 2

... ORDERING INFORMATION Device IR3087MTR IR3087M ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating……………………………………..HBM Class 1C JEDEC standard ...

Page 3

ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8.4V ≤ ≤ 14V, and 0 C ≤ T ≤ 125 J PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time GATEL low ...

Page 4

PARAMETER Ramp Comparator Input Offset Voltage Hysteresis RMPIN+, RMPIN- Bias Current Propagation Delay PWM Comparator PWM Comparator Input Offset Voltage EAIN & PWMRMP Bias Current Propagation Delay Common Mode Input Range Share Adjust Error Amplifier Input Offset Voltage Input Voltage ...

Page 5

PARAMETER OVP Comparator Threshold Voltage Propagation Delay General VCC Supply Current VCCL Supply Current VCCH Supply Current BIASIN Bias Current DACIN Bias Current VRHOT Comparator HOTSET Bias Current Output Voltage VRHOT Leakage Current Threshold Hysteresis Threshold Voltage Note 1: Guaranteed ...

Page 6

PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 RMPIN+ Non-inverting input to Ramp Comparator 2 RMPIN- Inverting input to Ramp Comparator 3 HOTSET Inverting input to VRHOT comparator. Connect resistor divider from VBIAS to LGND to program VRHOT threshold. Diode ...

Page 7

SYSTEM THEORY OF OPERATION TM XPhase Architecture TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control ...

Page 8

PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...

Page 9

VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is ...

Page 10

PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...

Page 11

Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...

Page 12

IR3087 THEORY OF OPERATION Block Diagram The Block diagram of the IR3087 is shown in Figure 6, and specific features are discussed in the following sections. RAMP COMPARATOR RMPIN+ CLOCK + PULSE RMPIN- - GENERATOR EAIN PWMRMP RAMP SLOPE ADJUST ...

Page 13

When designing for OVP the overall system must be considered. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB ...

Page 14

APPLICATIONS INFORMATION 12V RVCC 10 ohm RGATE CVCC 0.1uF 0.1uF ENABLE 1 21 OSCDS VBIAS VID5 2 20 VID5 BBFB VID0 3 IR3081A 19 VID0 EAOUT VID1 4 CONTROL 18 VID1 FB VID2 VID2 VDRP VID3 6 ...

Page 15

DESIGN PROCEDURES - IR3081A AND IR3087 CHIPSET IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081A generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...

Page 16

Over Current Setting Resistor R The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation ...

Page 17

IR3087 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP PWM ramp is generated by connecting the resistor R as the capacitor C between PWMRMP and LGND. Choose the desired PWM ramp magnitude V PWMRMP and the capacitor C ...

Page 18

Phase Delay Timing Resistors R The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of ...

Page 19

Opti-Phase Resistors R and R OP1 A resistor divider is used to program OPTIPHS pin voltage, which represents the load current threshold below which the phase is shut down to reduce the switching loss. Pre-select R (25), where I is ...

Page 20

Type II Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor ...

Page 21

Type III Compensation for Non-AVP Applications Resistor R is chosen according to Equations (13), and resistor R FB the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin θc. Calculate ...

Page 22

DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ADC OMAX ...

Page 23

SINK = = C VDAC − − DOWN Calculate the programming resistor. − ...

Page 24

IR3087 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP ∗ ∗ ∗ [ln PWMRMP . − 3 ...

Page 25

Opti-Phase Resistors R and R OP1 Disable Opti-phase function for phase 1 to keep it running at any load condition. Set the Opti-Phase shedding current threshold for phases Pre-select R ∗ ∗ ...

Page 26

DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ...

Page 27

I 170 * 10 SINK = = C VDAC − − DOWN Calculate the programming resistor. − ...

Page 28

IR3087 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP [ln PWMRMP = − ∗ ∗ ...

Page 29

R =10kΩ, R =768Ω, R PHASE41 PHASE42 Bootstrap Capacitor C BST Choose C =0.1uF BST Decoupling Capacitors for Phase IC and Power Stage Choose C =0.1uF, C =0.1uF VCC VCCL Opti-Phase Resistors R and R OP1 Disable Opti-phase function for ...

Page 30

CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop f loop f . Choose the crossover frequency of current share loop PWMRMP PWMRMP SW PWMRMP F MI ...

Page 31

LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is ...

Page 32

PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...

Page 33

Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...

Page 34

Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...

Page 35

PACKAGE INFORMATION 20L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ ...

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