ir3841 International Rectifier Corp., ir3841 Datasheet
ir3841
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ir3841 Summary of contents
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... PWM controller make IR3841 a space-efficient solution, providing accurate power delivery for low output voltage applications. IR3841 is a versatile regulator which offers programmability of start up time, switching frequency and current limit while operating in wide input and output voltage range. ...
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... PACKAGE DESIGNATOR M M 02/09/ Boot Gnd 14 Enable Seq FB COMP Gnd Rt PACKAGE PIN COUNT DESCRIPTION IR3841MTRPbF 15 IR3841MTR1PbF 15 IR3841MPbF o C and - PGnd θ θ PCB - PGood OCSet PARTS PER REEL ...
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... Block Diagram Fig. 2. Simplified block diagram of the IR3841 02/09/09 IR3841MPbF 3 ...
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... SW. Enable pin to turn on and off the device. Use two external resistors to 14 Enable set the turn on threshold (see Enable section). Connect this pin to Vcc not used. 15 Gnd Signal ground for internal reference and control circuitry. 02/09/09 IR3841MPbF Description 4 ...
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... C<Tj<125 C, Note3 SS=0V, No Switching, Enable low SS=3V, Vcc=5V, Fs=500kHz Enable high Vcc Rising Trip Level Vcc Falling Trip Level Supply ramping up and down Supply ramping up Supply ramping down Supply ramping up and down Enable=3.3V IR3841MPbF Max Units 16 5.5 V 5.5 0.9*Vin 8 A 1650 kHz o 125 ...
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... Test Condition Rt=59K Rt=28.7K Rt=9.31K, Note4 Note4 Note4 Note4 Note4 Fs=250kHz Vfb-Vseq, Vseq=0.8V Note4 Note4 Note4 Vcc=4.5V Note4 Source Fs=250kHz Fs=500kHz Fs=1500kHz Note4 I(Boot)=30mA IR3841MPbF <5.5V, V =12V C<T < 125 Min TYP MAX Units 0.665 0.7 0.735 V 225 250 275 450 500 550 ...
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... Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note4: Guaranteed by Design but not tested in production. 02/09/ Test Condition Note4 Note4 Fb Rising Relative to charge voltage, SS rising Note4 I =-5mA PGood SW=0V, Enable=0V SW=0V,Enable=high,SS=3V,Seq=0V, Note4 IR3841MPbF <5.5V, V =12V C<T < 125 Min TYP MAX 140 ...
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... IR3841MPbF C - 125 Icc(Dyn) - 100 ISS - 100 IOCSET (500k 100 [oC] ...
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... ETQP4LR36WFC 0.36 0.36 ETQP4LR36WFC ETQP4LR36WFC 1 1 MPL105-1R0 MPL105-1R0 1 1 MPL105-1R0 MPL105-1R0 1 1 MPL105-1R0 MPL105-1R0 rren t (A) 1.2V out 1.5V out 1.8V out 3.3V out rren t (A) 1.2V out 1.5V out 1.8V out 3.3V out IR3841MPbF DCR DCR (mΩ) (mΩ) 1.1 1.1 1.1 1.1 1.1 1.1 2.5 2.5 2.5 2.5 2.5 2 out out 9 ...
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... For all the output voltages, L=0.51uH (DCR=0.29 mΩ, P/N: 59PR9876N 1.0 1.5 2.0 2.5 0.7Vout 1.2Vout 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0 0.7Vout 1.2Vout 02/09/09 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Load Current (A) 0.75Vout 0.9Vout 1.0Vout 1.5Vout 1.8Vout 2.5Vout Load Current (A) 0.75Vout 0.9Vout 1.0Vout 1.5Vout 1.8Vout 2.5Vout IR3841MPbF 6.5 7.0 7.5 8.0 1.1Vout 3.3Vout 7 8 1.1Vout 3.3Vout 10 ...
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... MOSFETs using Fig. 3a. Normal Start up, Device turns on when the Bus voltage reaches 10.2V Figure 3b. shows the recommended start-up sequence for the non-sequenced operation of IR3841, when Enable is used as a logic input. Fig. 3b. Recommended startup sequence, IR3841MPbF . This is desirable particularly in exceeds the desired output voltage level. ...
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... Figure 3c. shows the recommended startup sequence for sequenced operation of IR3841 with Enable used as logic input. Fig. 3c. Recommended startup sequence, Sequenced operation Pre-Bias Startup IR3841 is able to start up into pre-charged output, which prevents disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated ...
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... Shutdown The IR3841 can be shutdown by pulling the Enable pin below its 1 V threshold. This will tri- state both, the high side driver as well as the low side driver. Alternatively, the output shutdown by pulling the soft-start pin below 0.3V. In shutdown by this method, the high side driver is turned off, and the low side driver is turned on ...
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... Thermal Shutdown Temperature sensing is provided inside IR3841. The trip threshold is typically set to 140 trip threshold is exceeded, thermal shutdown turns off both MOSFETs and discharges the soft start capacitor. Automatic restart is initiated when the sensed temperature drops within the operating range. o There hysteresis in the thermal shutdown threshold ...
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... TIMING DIAGRAM OF PGOOD FUNCTION Fig.9a IR3841 Non-Sequenced Operation (Seq=Vcc) 02/09/09 Fig.9b IR3841 Sequencing Operation IR3841MPbF 15 ...
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... Maximum Duty Ratio Considerations A fixed off-time of 200 ns maximum is specified for the IR3841. This provides an upper limit on the operating duty ratio at any given switching frequency clear, that higher the switching frequency, the lower is the maximum duty ratio at which the IR3841 can operate. To allow some ...
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... When an external resistor divider is connected to the output as shown in figure 11. Equation (5) can be rewritten as For the calculated values of R8 and R9 see feedback compensation section. Fig. 11. Typical application of the IR3841 for Soft-Start Programming V in The soft-start timing can be programmed by selecting the soft-start capacitance value. From R ...
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... SW L − PGnd = L Where: If Δi ≈ 35%(I calculated to be 0.91μH. Select L=1 μH. ....(12) The MPL105-1R0 from Delta provides a compact, low profile inductor suitable for this application. = 2.86A. . IR3841MPbF Δ The optimum operating ripple current Δ ∗ Δ = ∗ ...
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... The IR3841 can perform well with all types of capacitors rule, the capacitor must have low enough ESR to meet output ripple and load transient requirements. The goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size ...
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... III compensation network. The typically used compensation network for voltage-mode controller is shown in figure 15. Again, the transfer function is given by replacing Z .......... ....... (21) the transfer function can be expressed as IR3841MPbF = Zero Frequency of the Output Capacitor = % .......... .......... .......... 0 75 π ...
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... These result to ESR /2=300 kHz location of the F s Select crossover frequency: F Since F place the pole and zeros. IR3841MPbF Compensator Compensator ESR ESR o o Type Type Type II Type <F < ...
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... PGood pin, when the output voltage is not in regulation, to less than 5 mA. A typical value used is 4.7kΩ Select : C 150 Ω , Select : R 130 10 Ω Ω Select : R 2. IR3841MPbF ) from the SW pin OCSET R has a positive DS(on) ∗ OCSet OCSet = = I .......... .......... L ( critical ) 8.7 mΩ ...
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... OCSet 0.1uF 3.01k C3 1 150pF C4 1 10000pF R8 1 4.02K R9 1 2.55K R10 1 130 C7 1 2200pF U1 1 IR3841 02/09/ 330 uF Vin Boot 0 IR3841 2.67 K OCSet Comp PGnd Gnd 150 pF Description SMD Elecrolytic, Fsize, 25V, 20% 1206, 16V, X7R, 20% 11 ...
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... Fig. 19. Start up with 1.62V Pre Bias, 0A Load Fig. 21. Inductor node at 8A load Ch :LX 3 02/09/09 IR3841MPbF Fig. 18. Start Load Fig. 20. Output Voltage Ripple, 8A load out , Fig. 22. Short (Hiccup) Recovery ...
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... TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=0-8A, Room Temperature, No Air Flow 02/09/09 Fig. 23. Transient Response step out 4 out IR3841MPbF 25 ...
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... TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=1.8V, Io=8A, Room Temperature, No Air Flow Fig. 24. Bode Plot at 8A load shows a bandwidth of 111kHz and phase margin of 50 degrees 02/09/09 IR3841MPbF 26 ...
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... The inductor, output capacitors and the IR3841 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the Vin pin of IR3841. ...
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... SupIRBuck, kept away from noise sources. Fig.25c. IRDC3841 demoboard layout considerations – Mid Layer 1 Fig.25d. IRDC3841 demoboard layout considerations – Mid Layer 2 02/09/09 IR3841MPbF PGnd Power Vin Ground Plane AGnd Use separate traces for connecting Boot cap and Rocset to the ...
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... Pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper. 02/09/09 IR3841MPbF 29 ...
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... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. 02/09/09 IR3841MPbF 30 ...
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... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. 02/09/09 IR3841MPbF 31 ...
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... This product has been designed and qualified for the Consumer market 02/09/09 BOTTOM VIEW 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 01/09 IR3841MPbF TAC Fax: (310) 252-7903 32 ...