IRFPC50 Vishay, IRFPC50 Datasheet
IRFPC50
Specifications of IRFPC50
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IRFPC50 Summary of contents
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... TO-247 IRFPC50PbF SiHFPC50-E3 IRFPC50 SiHFPC50 = 25 °C, unless otherwise noted ° 100 ° °C C for screw = 25 Ω (see fig. 12 ≤ 150 ° IRFPC50, SiHFPC50 Vishay Siliconix device design, low on-resistance SYMBOL LIMIT V 600 DS V ± 7 1.4 E 920 ...
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... IRFPC50, SiHFPC50 Vishay Siliconix THERMAL RESISTANCE PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SPECIFICATIONS °C, unless otherwise noted J PARAMETER Static Drain-Source Breakdown Voltage V Temperature Coefficient DS Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance ...
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... TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig Typical Output Characteristics, T Fig Typical Output Characteristics, T Document Number: 91243 S-81369-Rev. A, 07-Jul- °C Fig Typical Transfer Characteristics C Fig Normalized On-Resistance vs. Temperature = 150 °C C IRFPC50, SiHFPC50 Vishay Siliconix www.vishay.com 3 ...
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... IRFPC50, SiHFPC50 Vishay Siliconix Fig Typical Capacitance vs. Drain-to-Source Voltage Fig Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 Fig Typical Source-Drain Diode Forward Voltage Fig Maximum Safe Operating Area Document Number: 91243 S-81369-Rev. A, 07-Jul-08 ...
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... Fig Maximum Drain Current vs. Case Temperature Fig Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91243 S-81369-Rev. A, 07-Jul-08 IRFPC50, SiHFPC50 Vishay Siliconix D.U. Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit d(on) r d(off) f Fig. 10b - Switching Time Waveforms www ...
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... IRFPC50, SiHFPC50 Vishay Siliconix Vary t to obtain p required I AS D.U. 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Charge Fig. 13a - Basic Gate Charge Waveform www.vishay.com Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 12b - Unclamped Inductive Waveforms Current regulator Same type as D.U.T. ...
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... SD • D.U.T. - device under test P.W. Period D = Period P.W. waveform SD Body diode forward current dI/dt waveform DS Diode recovery dV/dt Body diode forward drop Ripple ≤ for logic level devices Fig For N-Channel IRFPC50, SiHFPC50 Vishay Siliconix + + www.vishay.com 7 ...
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... Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’ ...