ISL1218 Intersil Corporation, ISL1218 Datasheet

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... Low Power RTC with Battery Backed SRAM The ISL1218 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user SRAM. The oscillator uses an external, low-cost 32.768kHz crystal. ...

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... The Serial Clock (SCL) input is used to clock all serial data into and out of the device. 7 IRQ/F Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The OUT function is set via the configuration register Power supply. DD ISL1218 INTERFACE CRYSTAL RTC OSCILLATOR DIVIDER POR ...

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... DD Serial Interface Specifications SYMBOL PARAMETER SERIAL INTERFACE SPECS V SDA and SCL Input Buffer LOW IL Voltage V SDA and SCL Input Buffer HIGH IH Voltage ISL1218 Thermal Information Pins Thermal Resistance (Typical, Note 1) OUT + 0.5 (V Mode) Moisture Sensitivity for MSOP Package DD DD -0. 0.5 (V Mode) BAT ...

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... These are I C specific parameters and are not directly tested, however they are used during device testing to validate device specification write to register 08h should only be done if V ISL1218 Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS T = 25° ...

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... TIMING) SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A ISL1218 HIGH LOW t SU:DAT t HD:STA OUTPUTS Will be steady Will change from LOW to HIGH ...

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... FIGURE 1. I 2.4E-06 2.2E- 2.0E-06 1.8E-06 1.6E- 3.3V 1.4E-06 1.2E-06 1.0E-06 -40 -20 0 TEMPERATURE (°C) FIGURE TEMPERATURE DD1 2.1E-6 2.0E-6 1.9E-6 1.8E-6 1.7E-6 1.6E-6 1.5E-6 1.4E-6 1.3E-6 1.2E-6 F OUT (Hz) FIGURE DD1 ISL1218 Temperature is +25°C unless otherwise specified 3.5 4.0 4.5 5.0 5.5 ( BAT BAT 3.3V OUT DD 6 1E-6 800E-9 600E-9 400E-9 200E-9 000E+0 -40 - TEMPERATURE (°C) FIGURE 2 ...

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... X1, X2 The X1 and X2 pins are the input and output, respectively inverting amplifier. An external 32.768kHz quartz crystal is used with the ISL1218 to supply a timebase for the real time clock. Internal compensation circuitry provides high accuracy over the operating temperature range from -40°C to +85°C. This oscillator compensation network can ...

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... ISL1218 for years. Another option is to use a Super Cap for applications where month. See the Applications Section for more information. Normal Mode ( Battery Backup Mode BAT To transition from the following conditions must be met: ...

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... The frequency output can be enabled/disabled during battery backup mode using the FOBATB bit. General Purpose User SRAM The ISL1218 provides 8 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However should be noted that the I C bus is disabled in battery backup mode ...

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... USR8 USR87 10 ISL1218 instruction latches all clock registers into a buffer update of the clock does not change the time being read. A sequential read will not result in the output of data from the memory array. At the end of a read, the master supplies a stop condition to end the operation and free the bus ...

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... Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year, the year 2100 is not. The ISL1218 does not correct for the leap year in the year 2100. ...

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... There is a supply current saving of DD BAT BATHYS about 600nA when using LPMODE = “1” with V (See Typical Performance Curves: I LPMODE ON and OFF.) 12 ISL1218 >V , then no It should be noted that any writes to the LPMODE bit that BAT DD may put the device into Low Power Mode should be avoided if V ...

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... Note that these are typical values. BATTERY MODE ATR SELECTION (BMATR <1:0>) Since the accuracy of the crystal oscillator is dependent on the V /V operation, the ISL1218 provides the capability DD BAT to adjust the capacitance between V device switches between power sources. BMATR1 ...

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... Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 12). On power up of the ISL1218, the SDA pin is in the input mode. 2 All I ...

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... The ISL1218 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The SCL SDA SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER SIGNALS FROM ...

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... Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL1218 responds with an ACK. Then the ISL1218 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 16) ...

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... ISL1218 In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the ISL1218. There are 3 bits known as the Digital Trimming Register (DTR). The range provided is ±60ppm in increments of 20ppm. DTR operates by adding or skipping pulses in the clock counter very useful for ...

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... A Super Capacitor can be used as an alternative to a battery in cases where shorter backup times are required. Since the battery backup supply current required by the ISL1218 is extremely low possible to get months of backup operation using a Super Capacitor. Typical capacitor values are a few µ Farad or more depending on the application ...

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... BAT voltage from fully charged to loss of operation. Note that I is the total of the supply current of the ISL1218 (I TOT plus the leakage current of the capacitor and the diode these calculations assumed to be extremely small LKG and will be ignored ...

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... B - 10. Datums -A - and to be determined at Datum plane . - H - 11. Controlling dimension: MILLIMETER. Converted inch dimen- sions are for reference only. 20 ISL1218 M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE θ 0.25 R1 (0.010 -C- 4X θ ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 ISL1218 M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE 0.25(0.010) ...