isl22323 Intersil Corporation, isl22323 Datasheet
isl22323
Available stocks
Related parts for isl22323
isl22323 Summary of contents
Page 1
... The ISL22323 also has 13 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22323 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometers or ...
Page 2
... RW0 GND 14 VCC GND 10 SCL 9 SDA 8 V- RH0 RH1 WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RL0 RW1 RL1 ISL22323 (16 LD QFN) TOP VIEW RL0 RH0 VCC FN6422.0 May 31, 2007 ...
Page 3
... EPAD* * Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 ISL22323 RH0 “High” terminal of DCP0 RL0 “Low” terminal of DCP0 RW0 “Wiper” terminal of DCP0 RH1 “High” terminal of DCP1 RL1 “ ...
Page 4
... FSerror Full-scale error (Note 7) V DCP to DCP matching MATCH (Note 10, 18) 4 ISL22323 Thermal Information Thermal Resistance (Typical, Note 3) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature (Plastic Package +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp ...
Page 5
... CC2 CC write/read Supply Current (non-volatile V-2 write/read) V- Supply Current (non-volatile write/read) 5 ISL22323 TEST CONDITIONS DCP register set to 80 hex Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) W option U, T option W option U, T option W option ...
Page 6
... DCP recall time from shut-down mode SCL falling edge of last bit of ACR data byte ShdnRec (Note 18) Vpor Power-on recall voltage VCCRamp V ramp rate CC t Power-up delay D 6 ISL22323 TEST CONDITIONS +5.5V -5.5V @ +85° interface in standby state +5.5V -5.5V @ +125° ...
Page 7
... SDA and SCL rise time R (Note 18) t SDA and SCL fall time F (Note 18) 7 ISL22323 TEST CONDITIONS Temperature T ≤ +55°C Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30 until CC SDA exits the 30 window ...
Page 8
... This parameter is not 100% tested. 19 the time from a valid STOP condition at the end of a Write sequence write cycle. 8 ISL22323 TEST CONDITIONS Total on-chip and off-chip Maximum is determined For Cb = 400pF, max is about 2~2.5kΩ For Cb = 40pF, max is about 15~20kΩ ...
Page 9
... SDA A0, A1 Typical Performance Curves 100 150 TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW FOR 10kΩ (W) CC TOTAL 9 ISL22323 10pF HIGH LOW t SU:DAT t HD:DAT CLK 1 t SU:A 2 +125ºC 1.5 1 +25ºC 0.5 -0 -40º ...
Page 10
... TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE 0 5.5V CC 0.25 0 -0. 2.25V CC -0. 100 150 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 10 ISL22323 (Continued) 0. +25ºC 0.25 0 -0.25 -0.50 200 250 0 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER 0 10k - 5. ...
Page 11
... TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm SCL WIPER FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h 11 ISL22323 (Continued) 200 10k 160 120 80 40 50k 0 80 120 FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm 50k ...
Page 12
... C monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL22323 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WRi will be reloaded with the value stored in corresponding non-volatile Initial Value Register (IVRi) ...
Page 13
... Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are N/A reserved for indicating START and STOP conditions (See N/A Figure 16). On power-up of the ISL22323, the SDA pin is in N/A the input mode. WR1 2 All I ...
Page 14
... THE SLAVE S SIGNALS T FROM THE A IDENTIFICATION MASTER R BYTE WITH T R SIGNAL AT SDA SIGNALS FROM K THE SLAVE 14 ISL22323 DATA DATA DATA STABLE CHANGE STABLE 1 WRITE IDENTIFICATION ADDRESS R BYTE BYTE ...
Page 15
... A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22323 responds with an ACK. At this time, the device enters its standby state (See Figure 18). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write ...
Page 16
... OUT 150k RH1 RW1 R 5 309, 1% 50k RL1 DCP1 (1/2 ISL22323U) PROGRAMMABLE GAIN 90 TO 110 R 6 1.37k, 1% ISL22323UFV14Z 14 1 VCC RH0 2 DCP0 RL0 10 3 SCL RW0 9 SDA 4 7 RH1 DCP1 RL1 A1 6 ...
Page 17
... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 17 ISL22323 L16.4x4A 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL MIN 0. θ - NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...
Page 18
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 ISL22323 M14.173 M B ...