isl22343 Intersil Corporation, isl22343 Datasheet

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isl22343

Manufacturer Part Number
isl22343
Description
Quad Digitally Controlled Potentiometer Xdcp? , Low Noise, Low Power, I2c? Bus, 256 Taps
Manufacturer
Intersil Corporation
Datasheet

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Low Noise, Low Power, I
The ISL22343 integrates four digitally controlled
potentiometers (DCP), control logic and non-volatile memory
on a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
corresponding wiper. At power up the device recalls the
contents of the DCP’s IVRi to the correspondent WRi.
The ISL22343 also has 11 general purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
The ISL22343 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
between V- and VCC.
Each DCP can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Ordering Information
NOTES:
ISL22343TFV20Z
ISL22343TFR20Z
ISL22343UFV20Z
ISL22343UFR20Z
ISL22343WFV20Z
ISL22343WFR20Z
2
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
2. Add “-TK” suffix for 1,000 Tape and Reel option
C bus interface. The potentiometer has an associated
PART NUMBER
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
(Notes 1, 2)
22343 TFVZ
22343 TFRZ
22343 UFVZ
22343 UFRZ
22343 WFVZ
22343 WFRZ
PART MARKING
®
1
2
Quad Digitally Controlled Potentiometer (XDCP™)
C
Data Sheet
®
Bus, 256 Taps
1-888-INTERSIL or 1-888-468-3774
RESISTANCE
OPTION
(kΩ)
100
100
50
50
10
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
TEMPERATURE
Features
• Four potentiometers in one package
• 256 resistor taps
• I
• Non-volatile EEPROM storage of wiper position
• 11 General Purpose non-volatile registers
• High reliability
• Wiper resistance: 70Ω typical @ 1mA
• Standby current <4µA max
• Shutdown current <4µA max
• Dual power supply
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40°C to +125
• 20 Lead TSSOP or 20 Lead QFN
• Pb-free plus anneal product (RoHS compliant)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
|
- Three address pins, up to eight devices per bus
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ +55
- VCC = 2.25V to 5.5V
- V- = -2.25V to -5.5V
2
RANGE
Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
C serial interface
(°C)
All other trademarks mentioned are the property of their respective owners.
May 31, 2007
20 Ld TSSOP
20 Ld QFN
20 Ld TSSOP
20 Ld QFN
20 Ld TSSOP
20 Ld QFN
Copyright Intersil Americas Inc. 2007. All Rights Reserved
PACKAGE
(Pb-free)
L20.5x5
L20.5x5
L20.5x5
M20.173
M20.173
M20.173
ISL22343
PKG. DWG. #
FN6423.0
°
C
°
C

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isl22343 Summary of contents

Page 1

... The ISL22343 also has 11 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22343 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometers or ...

Page 2

... VCC RH1 12 RL1 11 RW1 RH3 WR3 RW3 RL3 RH2 WR2 RW2 RL2 RH1 WR1 RW1 RL1 RH0 WR0 RW0 RL0 ISL22343 (20 LEAD QFN) TOP VIEW RW3 VCC 3 13 SCL SDA RH1 GND ...

Page 3

... EPAD* * Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 3 ISL22343 RH3 “High” terminal of DCP3 RL3 “Low” terminal of DCP3 RW3 “Wiper” terminal of DCP3 2 A2 Device address input for the I ...

Page 4

... FSerror Full-scale error (Note 7) V DCP to DCP matching MATCH (Note 10) 4 ISL22343 Thermal Information Thermal Resistance (Typical, Note 3) 20 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 +0 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Maximum Junction Temperature (Plastic Package +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp ...

Page 5

... CC volatile write/read Supply Current (non- V-2 volatile write/read) V- Supply Current (non- volatile write/read) 5 ISL22343 TEST CONDITIONS DCP register set to 80 hex Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) W option U, T option W option U, T option ...

Page 6

... Power-on recall voltage VCCRamp V ramp rate CC t Power-up delay D EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention t Non-volatile Write cycle WC (Note 19) time 6 ISL22343 TEST CONDITIONS +5.5V -5.5V @ +85° interface in CC standby state +5.5V -5.5V @ +125° interface in CC standby state +2.25V -2.25V @ +85°C, I ...

Page 7

... SDA and SCL rise time R (Note 18) t SDA and SCL fall time F (Note 18) 7 ISL22343 TEST CONDITIONS Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30 until SDA exits the CC 30 window CC SDA crossing 70 ...

Page 8

... This parameter is not 100% tested. 19 the time from a valid STOP condition at the end of a Write sequence write cycle. 8 ISL22343 TEST CONDITIONS Total on-chip and off-chip Maximum is determined by t and For Cb = 400pF, max is about 2~2.5kΩ For Cb = 40pF, max is about 15~20kΩ ...

Page 9

... R TOTAL 10pF 25pF RW SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A2, A1 and A0 Pin Timing START SCL SDA A2, A1 ISL22343 10pF HIGH LOW t SU:DAT t HD:DAT CLK SU:STO ...

Page 10

... TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 2.0 1.6 1.2 0.8 50k V = 2.25V CC 0 TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE 10 ISL22343 2 +125ºC 1.5 1 +25ºC 0.5 -0 -40ºC -1.0 -1.5 -2.0 200 250 FIGURE 2. STANDBY I 0. +25ºC 0.25 -0.25 -0.50 200 250 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER ...

Page 11

... FIGURE 9. END TO END R % CHANGE vs TOTAL TEMPERATURE 500 10k 400 300 200 100 116 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 11 ISL22343 (Continued) 2 +25ºC 1.5 1.0 0.5 -0.5 200 250 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 200 10k 160 120 80 40 ...

Page 12

... FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h Pin Description Potentiometers Pins RHi and RLi The high (RHi) and low (RLi) terminals of the ISL22343 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals ...

Page 13

... Data states on the SDA line must change only during SCL WR3 LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See WR2 Figure 16). On power-up of the ISL22343, the SDA pin is in WR1 the input mode. WR0 2 ...

Page 14

... During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 17). The ISL22343 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ...

Page 15

... A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22343 responds with an ACK. At this time, the device enters its standby state (See Figure 18). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write ...

Page 16

... ISL28272 OUT 3 FB FB- V- 150k RH1 RW1 R 5 309, 1% 50k RL1 DCP1 (1/4 ISL22343U) PROGRAMMABLE GAIN 90 TO 110 R 6 1.37k, 1% ISL22343UFV20Z 16 18 Vcc RH0 19 DCP0 RL0 5 20 SCL RW0 6 SDA 13 RH1 DCP1 RL1 ...

Page 17

... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) 17 ISL22343 L20.5x5 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0. θ - NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...

Page 18

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 ISL22343 M20.173 M B ...

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