ISL6265 Intersil Corporation, ISL6265 Datasheet
ISL6265
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ISL6265 Summary of contents
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... PART (Note) MARKING ISL6265HRTZ ISL6265 HRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6 ISL6265HRTZ-T* ISL6265 HRTZ -10 to +100 48 Ld 6x6 TQFN * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% ...
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... V0 1 ∑ NO MODE DROOP ISEN0 MODE CURRENT ISEN1 BALANCE NO DROOP MODE V1 ∑ 1 VREF1 E/A I_OFS FB1 COMP1 FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6265 2 FSET_NB PVCC I FSET_NB BOOT_NB FLT UGATE_NB MOSFET PHASE_NB DRIVER MODULATOR NB SHOOT-THRU LGATE_NB PROTECTION DE MODE PGND_NB VIN PSI_L PVCC VCC ...
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... Simplified Application Circuit for Dual Plane and Northbridge Support SVI DATA SVI CLOCK ENABLE PWROK www.DataSheet4U.com VDDPWRGD REMOTE SENSE REMOTE SENSE VDD_PLANE_STRAP FIGURE 2. ISL6265 BASED DUAL-PLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING ISL6265 +5V VIN VIN VCC PVCC GND SVD SVC UGATE0 EN ...
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... SVI DATA SVI CLOCK ENABLE PWROK www.DataSheet4U.com VDDPWRGD REMOTE SENSE REMOTE SENSE VDD_PLANE_STRAP OPEN OPEN OPEN OPEN FIGURE 3. ISL6265 BASED UNIPLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING ISL6265 +5V VCC PVCC VIN GND SVD UGATE0 SVC BOOT0 EN PWROK PHASE0 PGOOD ...
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... SVI DATA SVI CLOCK ENABLE PWROK www.DataSheet4U.com VDDPWRGD REMOTE SENSE VDD_PLANE_STRAP DNP DUAL PLANE REMOTE DNP UNIPLANE SENSE FIGURE 4. ISL6265 BASED UNIPLANE OR DUAL PLANE CORE CONVERTER WITH INDUCTOR DCR CURRENT SENSING ISL6265 +5V VCC PVCC VIN GND SVD UGATE0 SVC BOOT0 EN PWROK ...
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... NB Frequency Adjustment Range AMPLIFIERS (Note 3) Error Amp DC Gain Error Amp Gain-Bandwidth Product Error Amp Slew Rate ISL6265 Thermal Information Thermal Resistance (Typical, Notes 1, 2) θ Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below Recommended Operating Conditions Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . .+5V ± ...
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... LGATE Source Current (Note 4) LGATE Sink Resistance (Note 4) LGATE Sink Current (Note 4) UGATE to PHASE Resistance (Note 3) GATE DRIVER SWITCHING TIMING (Note 3) (Refer to “ISL6265 Gate Driver Timing Diagram” on page 8) UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time ...
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... SVD Low Level Output Voltage SVC, SVD Leakage (Note 3) DIFF AMP Accuracy NOTES: 3. Limits should be considered typical and are not production tested. 4. Limits established by characterization and are not production tested. ISL6265 Gate Driver Timing Diagram PWM UGATE LGATE t FL ISL6265 VCC = PVCC = 5V 12V -10° ...
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... C protocol is running. While this pin is low, the SVC, SVD, and VFIXEN input states determine the pre-PWROK metal VID or VFIX mode voltage. This pin must be low prior to the ISL6265 PGOOD output going high per the AMD SVI Controller Guidelines. PGOOD Controller power-good open-drain output. This pin is typically pulled up externally by a 2.0kΩ ...
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... PWM while eliminating many of their shortcomings. The ISL6265 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulse widths. Operating on these large-amplitude, noise-free synthesized signals allows the ISL6265 to achieve lower 3 modulator FN6599.0 May 7, 2008 ...
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... SVC and SVD pins to determine the soft-start target output voltage level. Power-On Reset The ISL6265 requires a +5V input supply tied to VCC and PVCC to exceed a rising power-on reset (POR) threshold before the controller has sufficient bias to guarantee proper operation ...
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... Interval locks core output configuration and pre-Metal VID code. All outputs soft-start to this level. Interval PGOOD signal goes HIGH indicating proper operation. Interval CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265 to prepare for SVI code. Interval SVC and SVD data lines communicate change in VID code. ...
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... PGOOD is pulled low. The pre-PWROK metal VID code is not retained. VID-on-the-Fly Transition Once PWROK is high, the ISL6265 detects this flag and begins monitoring the SVC and SVD pins for SVI instructions. The microprocessor will follow the protocol outlined in the following sections to send instructions for VID-on-the-Fly transitions ...
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... NOTE: Indicates a VID not required for AMD Family 10h processors. ISL6265 2 C bus concept. Two TABLE 3. SERIAL VID CODES SVID[6:0] VOLTAGE (V) SVID[6:0] 010_0000b 1.1500 100_0000b 010_0001b 1.1375 100_0001b 010_0010b 1.1250 ...
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... VID command applies. The address byte must be configured according to Table 4. The processor then sends the write bit. After the write bit, if the ISL6265 receives a valid address byte, it sends the acknowledge bit. The processor then sends the PSI-L bit and VID bits during the data phase ...
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... Core and Northbridge regulators feature two different types www.DataSheet4U.com of current sense circuits. CORE CONTINUOUS CURRENT SENSE The ISL6265 provides for load current to be measured using either resistors in series with the individual output inductors or using the intrinsic series resistance of the inductors as shown in the applications circuits in Figures 2 and 3. The load current in a particular output is sampled continuously every switching cycle ...
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... GND and PGND pins. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage is positive with respect to the GND and PGND pins. The ISL6265 monitors the phase voltage when the low-side MOSFET is conducting inductor current to determine the direction of the inductor current. ...
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... Power Good Signal The power-good pin (PGOOD open-drain logic output that signals if the ISL6265 is not regulating Core and Northbridge output voltages within the proper levels or output current in one or more outputs has exceeded the maximum current setpoint. ...
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... EN low or by bringing VCC below 3.9V. When these inputs are returned to their high operating levels, the controller soft-starts. The ISL6265 features a severe overvoltage (OV) threshold of 1.8V. If any of the outputs exceed this voltage fault is immediately triggered. PGOOD is latched low and the low-side MOSFETs of the offending output(s) are turned on ...
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... A DC/DC buck regulator must have output capacitance C into which ripple current I P-P a corresponding ripple voltage V sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of ISL6265 (EQ. 17) (EQ. 18) is selected based upon P-P (EQ. 19) O can flow. Current I ...
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... ----------------- - ⋅ η where η is converter efficiency Figure 12 provides the same input RMS current information for two-phase designs. 0.3 0 0.75 0.1 P-P 0.2 0.4 DUTY CYCLE (V FIGURE 12. NORMALIZED RMS INPUT CURRENT FOR 2-PHASE CONVERTER ISL6265 I = 0.50 P-P 0.75 P-P 0.25 P-P,N 0.5 0.6 0.7 0.8 0.9 1 IN/ O ⎞ ⋅ ⎠ (EQ ...
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... The bottom of the ISL6265 QFN package is the signal ground (GND) terminal for analog and logic signals of the IC. Connect the GND pad of the ISL6265 to the island of ground plane under the top layer using several vias, for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com ISL6265 FSET 23 FN6599 ...
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... Package Outline Drawing L48.6x6 48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 6 PIN 1 INDEX AREA www.DataSheet4U.com 0.15 (4X TYP ) ( TYPICAL RECOMMENDED LAND PATTERN ISL6265 6. TOP VIEW MAX 0. 48X 48X NOTES: 1. Dimensions are in millimeters. Dimensions ...