ISL6525 Intersil Corporation, ISL6525 Datasheet
ISL6525
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ISL6525 Summary of contents
Page 1
... TM Data Sheet Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller The ISL6525 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications designed to drive two N Channel MOSFETs in a synchronous-rectified buck topology. The ISL6525 integrates all of the control, output adjustment, monitoring and protection functions into a single package ...
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... Typical Application SS RT REF FB Block Diagram OCSET REFERENCE FB COMP RT 2 ISL6525 12V VCC OCSET MONITOR AND PROTECTION BOOT OSC UGATE PHASE ISL6525 PVCC +12V LGATE - + + PGND - COMP GND POWER-ON 110% RESET (POR 90 OVER- CURRENT 200 A 4V PWM COMPARATOR DACOUT + + - - ERROR AMP ...
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... Lower Gate Sink PROTECTION OCSET Current Source Soft Start Current PGOOD DELAY Discharge Current Source NMOS gate threshold voltage 3 ISL6525 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s 300 ...
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... COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. 4 ISL6525 ...
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... Programming PGOOD Delay Time section for more information. Functional Description Initialization The ISL6525 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage at the VCC pin and the input voltage ( the OCSET pin ...
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... inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6525 must be sized to handle peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane ...
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... The compensation network consists of the error amplifier (internal to the ISL6525) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin ...
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... Given a sufficiently fast control loop design, the ISL6525 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the lower MOSFETs body diode. The gate-charge losses are dissipated by the ISL6525 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, t which increases the upper SW MOSFET switching losses ...
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... Q2 - Intersil MOSFET; HUF76129D 10 ISL6525 V OUT C DELAY 1000pF VCC PGOOD DELAY OCSET 2 MONITOR AND 4.99K PROTECTION 10 BOOT Q1 9 UGATE OSC U1 PHASE 8 ISL6525 REF VCC 13 LGATE - PGND COMP GND 33pF 20K SPARE FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT 1 F 1N4148 0 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 11 ISL6525 M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE SYMBOL A ...