ISL6540 Intersil Corporation, ISL6540 Datasheet
ISL6540
Available stocks
Related parts for ISL6540
ISL6540 Summary of contents
Page 1
... An external voltage can be used in place of the internal reference for voltage tracking/DDR applications. The ISL6540 has an internal linear regulator or external linear regulator drive options for applications with only a single supply rail. The internal oscillator is adjustable from 250kHz to 2MHz. ...
Page 2
... Block Diagram 2 ISL6540 FN9214.0 March 9, 2006 ...
Page 3
... OFS- SS LINDRV ISL6540 BOOT BOOT VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540 C LSOC COMP VMON VSEN+ VSEN- GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT C BOUT Q2 10Ω ...
Page 4
... ISL6540 BOOT BOOT F1 VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540 C LSOC COMP VMON VCC VSEN+ VSEN- GND GND C HFIN C BIN C BOOT Q1 L OUT C BOUT C Q2 ...
Page 5
... OFS- OFS ISL6540 BOOT VCC PVCC BOOT R HSOC HSOC C HSOC UGATE PHASE LGATE PGND R LSOC LSOC ISL6540 C LSOC COMP VMON VSEN+ VSEN- LINDRV GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT ...
Page 6
... V EN_REF I Hysteresis Source Current EN_HYS V Maximum Input Voltage EN 6 ISL6540 Thermal Information Thermal Resistance (Note 1, 2) QFN Package (Note Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150° 0.3V Maximum Lead Temperature (Soldering 10s 300°C BOOT ...
Page 7
... Input Common Mode Range Max Input Common Mode Range Min V VSEN- Disable Voltage VSEN_DIS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain Drive Capability 7 ISL6540 TEST CONDITIONS GBD FS = 250kHz, 600 kHz, VFF = 3.3V to 20V FS = 250kHz, 600 kHz, VFF = 3.3V to 20V VCC = 5V Leading and Trailing-edge Modulation Leading and Trailing-edge Modulation REFIN = 0. 1µ ...
Page 8
... PG_DLY V PGOOD Delay Threshold Voltage PG_DLY I PGOOD Low Output Voltage PG_LOW I Maximum Sinking Current PG_MAX V Maximum Open Drain Voltage PG_MAX 8 ISL6540 TEST CONDITIONS 500mA Source Current, PVCC = 5. 2.5V, PVCC = 5.0V UGATE-PHASE 500mA Sink Current, PVCC = 5. 2.5V, PVCC = 5.0V UGATE-PHASE 500mA Source Current, PVCC = 5. 2.5V, PVCC = 5.0V LGATE 500mA Sink Current, PVCC = 5 ...
Page 9
... OFS+ and OFS- pins translates to a -200mV offset of the system reference. VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL6540 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry ...
Page 10
... F capacitor developed across the low side MOSFET when on. The sinking current limit is set the nominal sourcing limit in ISL6540. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. FS (Pin 24) This pin provides oscillator switching frequency adjustment ...
Page 11
... The POR function activates the internal 38µA OTA which begins charging the external capacitor (C target voltage of VCC. The ISL6540’s soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the low side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor ...
Page 12
... Number of low side MOSFETs L The ISL6540’s sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed 12 ISL6540 across the resistor (R triggered. To avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit ...
Page 13
... See the ISL6605 datasheet for specification parameters that are not defined in the current ISL6540 electrical specifications table. A 1-2Ω resistor is recommended series with the TO GND) T bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the phase node ...
Page 14
... OFS increased. In both modes the voltage difference between OFS+ and OFS- is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL6540 is ±200mV, this sets the MINIMUM value approximately 5.9K ...
Page 15
... Figure 8 should be located as close together as possible. Please note that the capacitors C and C O Locate the ISL6540 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6540 must be sized to handle peak current. ...
Page 16
... FB ISL6540 FIGURE 10. VOLTAGE-MODE BUCK CONVERTER The compensation network consists of the error amplifier (internal to the ISL6540) and the external R components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F phase margin (better than 45°). Phase margin is the ...
Page 17
... C is chosen so the corresponding SEN time constant does not reduce the overall phase margin of the design, typically this 10x switching frequency of the regulator. As the ISL6540 supports 100% duty cycle, d equals 1. The ISL6540 also uses MAX feedforward compensation, as such V 0.16 multiplied by the voltage at the VFF pin. When tieing ...
Page 18
... Given a sufficiently fast control loop design, the ISL6540 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
Page 19
... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 ISL6540 MOSFET Selection/Considerations The ISL6540 requires 2 N-Channel power MOSFETs. These should be selected based upon r 0.5Io requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors ...
Page 20
... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 20 ISL6540 L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE SYMBOL 0. ...