ISL8200MEVAL1PHZ Intersil, ISL8200MEVAL1PHZ Datasheet

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ISL8200MEVAL1PHZ

Manufacturer Part Number
ISL8200MEVAL1PHZ
Description
EVAL BAORD FOR ISL8200
Manufacturer
Intersil
Series
-r
Datasheets

Specifications of ISL8200MEVAL1PHZ

Main Purpose
DC/DC, Step Down
Outputs And Type
1, Non-Isolated
Power - Output
-
Voltage - Output
0.6 ~ 6 V
Current - Output
10A
Voltage - Input
3 ~ 20 V
Regulator Topology
Buck
Frequency - Switching
700kHz ~ 1.5MHz
Board Type
Fully Populated
Utilized Ic / Part
ISL8200
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Complete Current Share 10A DC/DC Power Module
ISL8200M
The ISL8200M is a simple and easy to use high power,
current-sharing DC\DC power module for
Datacom\Telecom\FPGA power hungry applications. All
that is needed is the ISL8200M, a few passive
components and one V
complete 10A design ready for market.
The ease of use virtually eliminates the design and
manufacturing risks while dramatically improving time
to market.
Need more output current? Just simply parallel up to six
ISL8200M modules to scale up to a 60A solution (see
Page 7, Figure 6).
The simplicity of the ISL8200M is in its "Off The Shelf",
unassisted implementation. Patented current sharing
in multi-phase operation greatly reduces ripple
currents, BOM cost and complexity.
The ISL8200M’s thermally enhanced, compact QFN
package, operates at full load and over-temperature,
without requiring forced air cooling. It's so thin it can
even fit on the back side of the PCB. Easy access to all
pins with few external components, reduces the PCB
design to a component layer and a simple ground
layer.
Complete Functional Schematic
February 26, 2010
FN6727.1
FIGURE 1. COMPLETE 10A DESIGN, JUST SELECT R
V
3V to 20V
IN
V
Range
EN
FOR THE DESIRED V
V
PV
EN
I
FF
SHARE
IN
IN
5k
ISL8200M
OUT
Module
Power
1
setting resistor to have a
OUT
V
V
SEN_REM
10 F
OUT_SET
P
V
GND1
1-888-INTERSIL or 1-888-468-3774
OUT
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
0.6V to 6.0V
V
OUT
R
SET
Range
SET
Features
• Complete Switch Mode Power Supply in One Package
• Patented Current Share Architecture Reduces Layout
• Programmable Phase Shift (1 to 6 phase)
• Extremely Low Profile (2.2mm height)
• Input Voltage Range +3.0 V to +20V at 10A, Current
• A Single Resistor Sets V
• Output Overvoltage, Overcurrent and
Applications*
• Servers, Telecom and Datacom Applications
• Industrial and Medical Equipment
• Point of Load Regulation
Related Literature*
• iSim Model - (See Respective Device Information
ISL8200M Package
Sensitivity When Modules are Paralleled
Share up to 60A
Over-Temperature, Built-in Protection and
Undervoltage indication
AN1544
User’s Guide
Page at http//:www.intersil.com)
FIGURE 2. THE 2.2mm HEIGHT IS IDEAL FOR THE
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
ISL8200MEVAL2PHZ Evaluation Board
BACKSIDE OF PCBS WHEN SPACE AND
HEIGHT IS A PREMIUM
(see page 21)
OUT
from +0.6V to +6V
(see page 21)
2.2mm

Related parts for ISL8200MEVAL1PHZ

ISL8200MEVAL1PHZ Summary of contents

Page 1

... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. from +0.6V to +6V ...

Page 2

... These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...

Page 3

Pin Configuration Pin Descriptions PIN NUMBER PIN NAME 1 VOUT_SET Analog Voltage Input - Used with V impedance of VSEN1+ with respect to VSEN1- is 500kΩ. Voltage input typ. 0.6V. 2 VSEN_REM- Analog Voltage Input - This pin is the ...

Page 4

Pin Descriptions (Continued) PIN NUMBER PIN NAME 6 ISHARE Analog Current Output - Cascaded system level over current shutdown pin. This pin is used where you have multiple modules configured for current sharing and is used with a common current ...

Page 5

Pin Descriptions (Continued) PIN NUMBER PIN NAME 21 VCC Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to 5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow ...

Page 6

Typical Application Circuits J1 VIN1 R1 C3 8.25k 270uF R2 2.05k J2 GND FIGURE 4. TWO PHASE 20A 1.2V OUTPUT CIRCUIT 6 ISL8200M (Continued) U201 ISL8200M PVIN C203 VIN 22uF FF C211 EN 1nF FSYNC_IN CLKOUT ISHARE_BUS ISFETDRV2 ISFETDRV RISHARE2 ...

Page 7

... ISL8200M Thermal Information Thermal Resistance (Typical) QFN Package (Notes Maximum Storage Temperature Range . . . -40°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below - 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp BOOT + 0.3V CC Recommended Operating Conditions + 0.3V CC Input Voltage, PVIN, V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . 3V to 5.6V Signal Bias Voltage, V ...

Page 8

Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL ...

Page 9

Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL ...

Page 10

VIN R1 CIN(CER) 16.5k 10uF 25V x 2 CIN (BULK) R2 4.12k GND FIGURE 5. TEST CIRCUIT FOR ALL PERFORMANCE AND DERATING GRAPHS Typical Performance Characteristics Efficiency Performance T The efficiency equation is: 100 3.3V 75 ...

Page 11

Typical Performance Characteristics Transient Response Performance V OUT I OUT FIGURE 10. 1.5V TRANSIENT RESPONSE V OUT I OUT FIGURE 12. 2.5V TRANSIENT RESPONSE 11 ISL8200M (Continued +25° 12V ...

Page 12

Typical Performance Characteristics Output Ripple Performance V 10A OUT V 5A OUT V 0A OUT FIGURE 14. 1.2V OUTPUT RIPPLE V 10A OUT V 5A OUT V 0A OUT FIGURE 16. 2.5V OUTPUT RIPPLE 12 ISL8200M (Continued +25°C, ...

Page 13

Typical Performance Curves FIGURE 18. 4-BOARD CLOCK SYNC (V Applications Information Programming the Output Voltage ( The ISL8200M has an internal 0.6V ± 0.7% reference voltage. Programming the output voltage requires a dividing resistor (R ) between VOUT_SET pin and ...

Page 14

The output voltage accuracy can be improved by maintaining the impedance at V OUTSET below 1kΩ effective impedance. Note: the SEN1+ impedance between V and V SEN1+ The module has minimum input voltage at a given ...

Page 15

A 1nF capacitor is recommended as a starting value for typical application. The voltage on the FF pin needs to be above 0.7V prior to soft-start and during PWM switching to ensure reliable regulation ...

Page 16

Power Good The Power-Good comparators monitor the voltage on the internal VMON1 pin. The trip points are shown in Figure 26. PGOOD will not be asserted until after the completion of the soft-start cycle. The PGOOD pulls low upon both ...

Page 17

OC trip set by 1.2V comparator can be lower than 108µA trip point as shown in Equation 6. ⎛ V ⎛ – OUT • ⎜ I --------------- - --------------- - T + – ⎝ OC MIN_OFF ⎝ L ...

Page 18

RFS-ext (kΩ) FIGURE 27. RFS-ext vs SWITCHING FREQUENCY By connecting the FSYNC_IN pin to an external square pulse waveform (such as the CLKOUT signal, typically 50% duty cycle ...

Page 19

LOAD CURRENT (A) FIGURE 29. POWER LOSS vs LOAD CURRENT (5V 5.0 4.5 5.0V 4.0 3.5 3.3V 3.0 2.5V 2.5 1.5V 0.8V 2.0 1.5 1.0 0.5 0.0 ...

Page 20

Thermal Vias A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter with the barrel ...

Page 21

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...

Page 22

Package Outline Drawing L23.15x15 23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 1, 12/ 15.0±0.2 ...

Page 23

TYPICAL RECOMMENDED LAND PATTERN 6.23 4.18 3.88 1.83 1.53 0.00 0.52 0.82 2.87 ...

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