ISL90843 Intersil Corporation, ISL90843 Datasheet
ISL90843
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ISL90843 Summary of contents
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... Low Noise, Low Power 256 Taps The ISL90843 integrates four digitally controlled potentiometers (XDCP monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the ...
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... SDA SCL A1 A0 Pin Descriptions MSOP PIN SYMBOL 1 RW3 2 SCL 3 SDA 4 GND 5 RW2 6 RW1 RW0 2 ISL90843 INTERFACE GND WR3 WR2 POWER-UP, INTERFACE, CONTROL AND STATUS LOGIC WR1 WR0 GND “ ...
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... I Leakage Current, at Pins A0, A1, LkgDig SDA and SCL Pins t DCP Wiper Response Time DCP (Note 15) Vpor Power-On Recall Voltage 3 ISL90843 Recommended Operating Conditions Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85° 2.7V to 5.5V CC +0.3 Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CC Wiper Current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CC TEST CONDITIONS ...
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... Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip (Note 15) Rpu SDA and SCL Bus Pull-Up (Note 15) Resistor Off-Chip 4 ISL90843 TEST CONDITIONS V above Vpor, to DCP Initial Value Register recall CC 2 completed, and I C Interface in Standby State. Any pulse narrower than the max spec is suppressed. ...
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... ⁄ 125°C Max Ri + Min Ri 15. This parameter is not 100% tested. 5 ISL90843 TEST CONDITIONS Before START condition After STOP condition HIGH LOW t SU:DAT t HD:DAT CLK 1 t SU:A and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the ...
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... Vcc = 5. 25°C -0.1 Vcc = 2. 85°C -0.15 -0 100 150 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION FOR 10kΩ (W) 0.4 0.35 0.3 2.7V 0.25 0.2 5.5V 0.15 -40 - TEMPERATURE (°C) FIGURE 5. ZSerror vs TEMPERATURE 6 ISL90843 1.8 1.6 Vcc = 2. 25°C 1.4 1.2 1.0 0.8 0.6 0.4 Vcc = 5. 85°C 0.2 0.0 200 250 0.3 Vcc = 2. -40°C 0.2 0.1 0 -0.1 Vcc = 5. 85°C -0.2 -0.3 200 250 -0 ...
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... RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL90843 is being powered up, all four WRs are reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WRs can be read or written directly using the I interface as described in the following sections ...
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... Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 11). On power-up of the ISL90843 the SDA pin is in the input mode. 2 All I ...
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... Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90843 responds with an ACK. At this time, the device enters its standby state (See Figure 13). 9 ISL90843 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 ISL90843 10 Lead MSOP, Package Code 0.0106 [0.27] 4 ...