isp1181b NXP Semiconductors, isp1181b Datasheet
isp1181b
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isp1181b Summary of contents
Page 1
... The result is fast and efficient development of the most cost-effective USB peripheral solution. The ISP1181B is ideally suited for application in many personal computer peripherals such as printers, communication devices, scanners, external mass storage (Zip drive) devices and digital still cameras. It offers an immediate cost reduction for applications that currently use SCSI implementations ...
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... Plastic thin shrink small outline package; 48 leads; body width 6.1 mm Plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 7 0.85 mm Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Version SOT362-1 SOT619-2 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... MANAGEMENT UNIT HANDLER INTEGRATED ENDPOINT RAM HANDLER INTERNAL I/O PIN 3.3 V SUPPLY SUPPLY 9 8 25, 36 ref WAKEUP GND V CC(3.3) to/from microcontroller 17 BUS_CONF0 18 BUS_CONF1 38 27, AD0 DATA1 to DATA9, BUS DATA10 to DATA15 INTERFACE CS, ALE, WR, RD INT ISP1181B 004aaa134 ...
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... SUSPEND 9 EOT 10 DREQ 11 DACK 12 ISP1181BDGG TEST1 13 TEST2 14 INT 15 TEST3 16 BUS_CONF0 17 BUS_CONF1 18 DATA15 19 DATA14 20 DATA13 21 DATA12 22 DATA11 23 DATA10 24 004aaa135 Rev. 02 — 07 December 2004 ISP1181B 48 XTAL1 47 XTAL2 46 GND 45 CLKOUT 44 RESET ALE AD0 V CC(3. GND 35 DATA1 34 DATA2 33 DATA3 32 DATA4 31 DATA5 ...
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... Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 25 DATA6 26 DATA5 27 DATA4 28 DATA3 29 DATA2 30 DATA1 ISP1181BBS 31 GND 32 V CC(3.3) 33 AD0 004aaa136 Description supply voltage (3 5.0 V) voltage regulator ground supply regulated supply voltage (3.3 V from internal regulator; used to connect decoupling capacitor and pull-up resistor on D line ...
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... DMA transfer to the ISP1181B O DMA request output (4 mA; programmable polarity, see Table 21); signals to the DMA controller that the ISP1181B wants to start a DMA transfer I DMA acknowledge input (programmable polarity, see Table 21); used by the DMA controller to signal the start of a DMA ...
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... Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Type Description I/O bit 5 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) I/O bit 4 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) I/O bit 3 of D[15:0]; bidirectional data line (slew-rate controlled output, 4 mA) I/O bit 2 of D[15:0] ...
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... HVQFN48 Symbol names with an overscore (for example, NAME) represent active LOW signals. Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Type Description - ground supply O crystal oscillator output (6 MHz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock ...
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... USB endpoints. The type and FIFO size of each endpoint can be individually configured, depending on the required packet size. Isochronous and bulk endpoints are double-buffered for increased data throughput. The ISP1181B requires a single supply voltage of 3 5.0 V and has an internal 3.3 V voltage regulator for powering the analog USB transceiver. It supports bus-powered operation. ...
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... ISP1181B has been successfully enumerated (the peripheral address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1181B, the LED will blink off for 100 ms. During ‘suspend’ state, the LED will remain off. ...
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... The ISP1181B has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable endpoints, which can be individually defined as interrupt/bulk/isochronous OUT. Each enabled endpoint has an associated FIFO, which can be accessed either via the parallel I/O interface or via DMA ...
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... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1181B transmits); OUT: output from the USB host (ISP1181B receives). The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register. ...
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... OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes ...
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... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1181B disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time ...
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... The ISP1181B supports DMA transfer for all 14 configurable endpoints (see Only one endpoint at a time can be selected for DMA transfer. The DMA operation of the ISP1181B can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • ...
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... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1181B in 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
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... The 8237 now sets its address lines to 1234H and activates the MEMW and IOR 6. The 8237 asserts DACK to inform the ISP1181B that it will start a DMA transfer. 7. The ISP1181B now places the byte or word to be transferred on the data bus 8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This 9 ...
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... Philips Semiconductors In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes ...
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... DMA operation is disabled by clearing bit DMAEN. Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller IN endpoint EOT is active transfer completes as programmed in the DMA Counter register counter reaches zero in the ...
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... All signals connected to the ISP1181B must enter appropriate states to meet the power consumption requirements of the suspend state. b. All input pins of the ISP1181B must have a CMOS LOW or HIGH level. USB bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed ...
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... B: indicates resume condition, which can K-state on the USB bus, a HIGH level on pin WAKEUP LOW level on pin CS. • C: indicates remote wake-up. The ISP1181B will drive a K-state on the USB bus for 10 ms after pin WAKEUP goes HIGH or pin CS goes LOW. • ...
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... The SUSPEND output is deasserted, and bit RESUME in the Interrupt register is 3. Maximum 15 ms after starting the wake-up sequence, the ISP1181B resumes its 4. In case of a remote wake-up, the ISP1181B drives a K-state on the USB bus for 5. Following the deassertion of output SUSPEND, the application restores itself and 6 ...
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... A complete access consists of two phases: 1. Command phase: when address bit the ISP1181B interprets the data on 2. Data phase (optional): when address bit the ISP1181B transfers the The following applies for register or FIFO access in 16-bit bus mode: • ...
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... FIFO endpoint (IN endpoints [5] only) FIFO endpoint 0 OUT [6] illegal FIFO endpoint [6] (OUT endpoints only) Endpoint 0 OUT Endpoint 0 IN Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller [1] Code (Hex) Transaction [2] 31 read 1 byte [ read 1 byte B6/B7 write/read 1 byte ...
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... Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1181B and to perform a device reset. 12.1.1 Write/Read Endpoint Configuration This command is used to access the Endpoint Confi ...
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... A logic 1 indicates that this endpoint has double buffering. FFOISO A logic 1 indicates an isochronous endpoint. A logic 0 indicates a bulk or interrupt endpoint. FFOSZ[3:0] Selects the FIFO size according R/W R/W Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 3 2 FFOSZ[3: R/W R/W R/W Table DEVADR[6:0] 0 ...
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... Write/Read Mode Register This command is used to access the ISP1181B Mode Register, which consists of 1 byte (bit allocation: see The Mode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
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... The hardware design guarantees no glitches during frequency change. Bus reset value: unchanged. DAKOLY A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237 compatible DMA mode. Bus reset value: unchanged. Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Table 20. A bus reset will not change any 11 10 ...
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... R/W R IEP12 IEP11 R/W R IEP4 IEP3 R/W R/W Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller …continued must be present). Bus reset BUS Section 13 for details. Bus reset value: unchanged R/W R/W R IEP10 IEP9 IEP8 R/W ...
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... Write/Read DMA Configuration This command defines the DMA configuration of ISP1181B and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The bit allocation is given in DMAEN (DMA disabled), all other bits remain unchanged. ...
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... Bus reset value: unchanged. Table 26. Writing to the register sets the number of bytes for DMACRH[7: R/W R DMACRL[7: R/W R/W Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Section 12.1.6 for more details R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Bit 12.1.8 Reset Device This command resets the ISP1181B in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 12.2 Data flow commands Data fl ...
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... D[15:0] data D[15:0] … … 31. Reading the Endpoint Status Register will clear the interrupt bit set for the Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Description packet length (lower byte) packet length (upper byte) data byte 1 data byte 2 … data byte N ...
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... Setup packet. SETUPT A logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller OVER SETUPT CPUBUF WRITE ...
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... A logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 A logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the next packet (0 = DATA0 PID DATA1 PID). Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Section Section Table 33. 3 ...
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... A logic 1 indicates that a new event occurred before the previous status was read. DATA01 This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID DATA1 PID). Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller …continued Section ...
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... Unlock Device This command unlocks the ISP1181B from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
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... SFIRL[7: R/W R/W Scratch Information Register: bit description Symbol Description - reserved; must be logic 0 SFIRH[6:0] Scratch Information Register (high byte) SFIRL[7:0] Scratch Information Register (low byte) Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller SFIRH[6: ...
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... Word # Description - command code (B4H) - ignored 0 frame number 11 10 81H R R © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B Table 46 ...
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... EP10 EP9 EP2 EP1 EOT SUSPND RESUME © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B EP8 EP7 EP0IN EP0OUT ...
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... USB bus. RESUME A logic 1 indicates that a ‘resume’ state was detected. RESET A logic 1 indicates that a bus reset condition was detected. shows the interrupt logic of the ISP1181B. Each of the indicated USB events Table 19). Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller … ...
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... Interrupt Register. SETUP and OUT token interrupts are generated after ISP1181B has acknowledged the associated data packet. In bulk transfer mode, the ISP1181B will issue interrupts for every ACK received for an OUT token or transmitted for an IN token. ...
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... The ISP1181B is powered from a single supply voltage, ranging from 4 5 integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the USB transceiver. This voltage is available at pin V external pull-up resistor on USB connection D . See The ISP1181B can also be operated from a 3 3.6 V supply, as shown in Figure be connected to V ISP1181B CC(3 ...
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... NOLAZY Fig 12. Oscillator and LazyClock logic. When ISP1181B enters ‘suspend’ state (by setting and clearing bit GOSUSP in the Mode Register), outputs SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0, the clock signal on output CLKOUT does not stop, but changes to the 100 kHz When resuming from ‘ ...
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... Philips Semiconductors 16. Power-on reset The ISP1181B has an internal power-on reset (POR) circuit. Input pin RESET can be directly connected to V power-on and normally requires stabilize. The triggering voltage of the POR circuit is 2.0 V nominal. A POR is automatically generated when V Fig 14. Power-on reset timing. ...
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... Product data Full-speed USB peripheral controller Conditions V < > [1] I < 5 Conditions Min with regulator 4.0 without regulator 3 Rev. 02 — 07 December 2004 ISP1181B Min Max Unit 0.5 6 100 mA - 2000 V 60 150 C - 165 mW Typ Max Unit 5 ...
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... amb must be connected to pin V . CC(3. unless otherwise specified. GND amb Conditions I = rated drive rated drive OH Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Min Typ Max [1] [2] 3.0 3 ...
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... unless otherwise specified. GND amb Conditions V V I(D ) I(D ) includes V range 1 3 GND L pin to GND SoftConnect = ON steady-state drive ) both D and reg(3.3) Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Min Typ Max 0 0 0.8 2 0.3 2 ...
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... see Figure 15 see Figure 15 see Figure 16 see Figure 16 accepted as EOP; see Figure 15 rejected as EOP; see Figure 17 Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Min Typ Max [ pF 1 ...
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... PERIOD JR1 paired transitions PERIOD JR2 3.3 V differential data lines 0 V Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller crossover point extended source EOP width: t receiver EOP width JR1 JR2 t FST V IH(min) mgr872 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... SHDZ after CS HIGH t chip deselect time after RD HIGH RHSH t RD pulse width RLRH t data valid time after RD LOW RLDV t CS HIGH until next ISP1181B RD SHRL read cycle time SHRL RLRH Write timing (see Figure 19) t address hold time after WR HIGH ...
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... Fig 19. Parallel interface write timing (I/O and 8237 compatible DMA). 9397 750 13958 Product data t RHAX t AVRL t SHDZ (1) t SHRL t RLRH t RHSH t WHAX t AVWL (1) t SHWL t WHSH t WHDZ Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller MGS787 MGS789 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Fig 21. Write command + write data cycle timing. 9397 750 13958 Product data LLAX t AVLL A0 Conditions Figure 21 and Figure 22) Figure 23 and Figure 24) command data T cy(WC-WD) Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller D0 8-bit bus 16-bit bus Min Max Min [1] 100 - 205 90 - 205 90 - 205 [1] 100 ...
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... DREQ off after DACK on ASRP T cycle time signal DREQ cy(DREQ) 9397 750 13958 Product data data command T cy(WD-WC) command data T cy(WC-RD) data command T cy(RD-WC) Conditions 25) Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller data (1) MGT025 data T cy(RD-RD) MGT023 data (1) MGT024 8-bit bus 16-bit bus Min Max Min - 40 - ...
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... Fig 25. DMA timing in 8237 compatible mode. 9397 750 13958 Product data …continued Conditions 8-bit bus Min 26 27 EOT on; 22 DACK on; RD/WR LOW - - T cy(DREQ) t ASRP Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 16-bit bus Max Min Max 180 - 180 - - 5 ...
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... Product data t ASRP t ASDV t ASAP t ASRP t DVAP t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller t APRS t APDZ MGS793 t APRS t APDZ MGS794 MGS795 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... DREQ DACK RD/WR Fig 29. Burst mode DMA timing. 9397 750 13958 Product data Conditions 8-bit bus Min EOT on; 22 DACK on; RD/WR LOW - - - t RSIH t IHIL Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 16-bit bus Max Min Max - 180 - - ...
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... The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW). Fig 30. EOT timing in burst mode DMA. 9397 750 13958 Product data Full-speed USB peripheral controller t ISRP t RLIS t WLIS (1) t EOT Rev. 02 — 07 December 2004 ISP1181B MGS797 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... DATA11 DATA12 DATA13 V BUS DATA14 DATA15 ISP1181B A0 ALE XTAL1 XTAL2 INT SUSPEND WAKEUP DREQ DACK EOT BUS_CONF1 BUS_CONF0 Rev. 02 — 07 December 2004 ISP1181B V CC LINK LED V CC 0.1 0 USB upstream connector MHz 004aaa143 © ...
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... INT SUSPEND WAKEUP DREQ DACK EOT BUS_CONF1 BUS_CONF0 8-BIT DMA PORT Rev. 02 — 07 December 2004 ISP1181B V CC LINK LED V reg(3. RESET 0.1 0 USB upstream connector V BUS XTAL1 XTAL2 GL 6 MHz ...
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... CS7 when external address space for the associated area is accessed. The ISP1181B can be mapped to any address area, allowing easy interfacing when the ISP1181B is the only peripheral in that area the example circuit for bus configuration mode 0 (see (in area 7), output CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181B. The external bus specifi ...
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... Philips Semiconductors 22.2.4 Using H8S/2357 I/O Ports In the interface circuit of general purpose output port. This pin drives the ISP1181B’s WAKEUP input to generate a remote wake-up. The H8S/2357 has 3 registers to configure port 1: Port 1 Data Direction Register (P1DDR), Port 1 Data Register (P1DR) and Port 1 Register (PORT1). Only registers P1DDR and P1DR must be confi ...
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... Rev. 02 — 07 December 2004 Full-speed USB peripheral controller detail 0.8 0.50 1 0.25 0.08 0.4 0.35 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B SOT362 0.8 8 0.1 o 0.4 0 ISSUE DATE 99-12-27 03-02- ...
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... Rev. 02 — 07 December 2004 Full-speed USB peripheral controller detail 2 scale 5.25 0.5 0.5 5.5 5.5 0.1 4.95 0.3 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B SOT619 0.05 0.05 0.1 ISSUE DATE 02-05-17 02-10- ...
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... C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 2.5 mm 350 called small/thin packages. © ...
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... Rev. 02 — 07 December 2004 Full-speed USB peripheral controller Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended [8] not suitable © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B [2] Reflow suitable suitable suitable suitable suitable not suitable ...
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... The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller 10 C measured in the atmosphere of the reflow © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Added parameters t RHAX WHAX Rev. 02 — 07 December 2004 Full-speed USB peripheral controller mode”: removed EOP from the paragraph before the and Table 21 “Hardware timing”: updated values for and t SHRL SHWL © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ISP1181B . ...
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... OnNow — trademark of Microsoft Corp. SoftConnect — trademark of Koninklijke Philips Electronics N.V. Zip — registered trademark of Iomega Corp. Rev. 02 — 07 December 2004 ISP1181B Full-speed USB peripheral controller Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.1 Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.2 Access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.3 DMA timing: single-cycle mode . . . . . . . . . . . . . . . . 54 21.4 DMA timing: burst mode . . . . . . . . . . . . . . . . . . . . . . 57 22 Application information . . . . . . . . . . . . . . . . . . . . . . . 59 22.1 Typical interface circuits . . . . . . . . . . . . . . . . . . . . . . 59 22.2 Interfacing ISP1181B with an H8S/2357 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.1 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.2 Address mapping in H8S/2357 . . . . . . . . . . . . . . . . . 61 22.2.3 Using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.4 Using H8S/2357 I/O Ports . . . . . . . . . . . . . . . . . . . . 62 23 Test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 24 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 25 Soldering ...