isp1504c NXP Semiconductors, isp1504c Datasheet
isp1504c
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isp1504c Summary of contents
Page 1
... ISP1504A; ISP1504C ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver Rev. 01 — 19 October 2006 1. General description The ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 , On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 and UTMI+ Low Pin Interface (ULPI) Specification Rev ...
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... Supports both 60 MHz input clock and 60 MHz output clock configurations N Integrated Phase-Locked Loop (PLL) with auto-configuring support for 60 MHz input clock, or one crystal or clock frequency: 19.2 MHz (ISP1504ABS) and 26 MHz (ISP1504CBS) N Fully programmable ULPI-compliant register set Internal Power-On Reset (POR) circuit ...
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... ISP1504CBS 504C 26 MHz [1] The package marking is the first line of text on the IC package and can be used for IC identification. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Package Name Description HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 HVQFN32 plastic thermal enhanced very thin quad flat package; ...
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... GLOBAL CLOCKS 15 XTAL1 16 XTAL2 2, 22, 30 interface voltage V CC(I/O) 14 REG3V3 18 REG1V8 Fig 1. Block diagram ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C USB DATA SERIALIZER ULPI INTERFACE CONTROLLER USB DATA DESERIALIZER DRV V BUS V VALID BUS ON-THE-GO MODULE EXTERNAL REGISTER MAP DRV V BUS EXTERNAL ...
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... AI/O FAULT CPGND 8 P C_B 9 AI/O C_A 10 AI PSW_N 12 OD ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C terminal 1 index area 1 DATA0 V 2 CC(I/O) 3 RREF DM 4 ISP1504 FAULT ID 7 CPGND 8 Transparent top view [4] Description pin 0 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down ...
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... For details on external components required on each pin, see bill of materials and application diagrams in [ input output; I/O = digital input/output open-drain output analog input analog output; AI/O = analog input/output power or ground pin. [4] A detailed description of these pins can be found in ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C [4] Description V pin of the USB cable BUS 5 V tolerant 3.3 V regulator output ...
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... USB bus in high-speed, full-speed and low-speed, for USB peripheral, host and OTG implementations. The following circuitry is included: • Differential drivers to transmit data at high-speed, full-speed and low-speed ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C charge pump or external source BUS Section Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver 9. © ...
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... The ID detector to sense the ID pin of the mini-USB cable. The ID pin dictates which device is initially configured as the host and which as the peripheral. ISP1504A_ISP1504C_1 Product data sheet CC Section 16. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Table 8. supply for use CC < 3.6 V © NXP B.V. 2006. All rights reserved. ...
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... DISCHRG_VBUS register bit to logic 1 and waiting for SESS_END to be logic 1. Then the B-device charges V register bit to logic 1. The A-device sees that V threshold and starts a session by turning on the V ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C voltage level. This is required for the V BUS . The downstream peripheral can draw its BUS . ...
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... V BUS 0.1 F ISP1504 C_B C cp(C_A)-(C_B) C_A Section 9.3.1. 16. V provides power to on-chip pads of the following pins: CC(I/O) Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver at a nominal voltage BUS depends on the cp(C_A)-(C_B) cp(C_A)-(C_B) 7.9.8. OTG V BUS 4.7 F 004aaa515 , resistor connected RREF Section 16 ...
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... ID pin must be connected to ground. 7.9.7 CPGND CPGND indicates the analog ground for the on-board charge pump. CPGND must always be connected to ground, even when the charge pump is not used. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C power. If the V CC CC(I/O) RREF Section 16. This provides an accurate voltage reference that ...
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... V BUS Section 16. BUS state in RXCMD is not 11b), it must disable the external BUS comparators, and also as a power pin for the charge BUS Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver C cp(C_A)-(C_B 004aaa516 I (max required when PSW_N is used ...
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... The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH. For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C pin ( must not be attached when using the ISP1504 BUS VBUS ...
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... This acts as a ground to all circuits in the ISP1504, except the charge pump. To ensure correct operation of the ISP1504, GND must be soldered to the cleanest ground available. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C 9.3.1. Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver Section 9.3.3. © ...
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... DIR changes value. This is called the turnaround cycle. Data lines have fixed direction and different meaning in low-power and serial modes. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Section 9. © NXP B.V. 2006. All rights reserved. ...
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... NXT is not used in low-power or serial mode. Description combinatorial LINESTATE0 directly driven by analog receiver combinatorial LINESTATE1 directly driven by analog receiver Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver supply (see Table 43). CC © NXP B.V. 2006. All rights reserved. ...
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... For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C …continued Description reserved; the ISP1504 will drive this pin to LOW active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs reserved ...
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... Host low-speed 10b 1b ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Description active HIGH transmit enable transmit differential data on DP and DM when TX_ENABLE is HIGH receive differential data from DP and DM when TX_ENABLE is LOW transmit single-ended zero on DP and DM when TX_ENABLE is HIGH receive single-ended zero from DP and DM when TX_ENABLE is LOW active HIGH interrupt indication ...
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... OTG device 01b 1b peripheral high-speed and full-speed suspend OTG device 01b 1b peripheral high-speed and full-speed resume OTG device 00b 0b peripheral Test J or Test K ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C …continued OPMODE DP_PULL DM_PULL [1:0] DOWN DOWN 00b 1b 1b 10b 1b 1b 10b 1b 1b 10b 0b ...
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... V w(REG1V8_L Figure PORP startup(o)(CLOCK) Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver , for at least POR(trip) again. The POR(trip) shows a possible curve of REG1V8. The before it PORP , another POR pulse is w(REG1V8_L) , the internal POR pulse ...
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... RESET command. • The ULPI interface is ready for use. ISP1504A_ISP1504C_1 Product data sheet Figure crystal is attached and a 60 MHz clock is driven into the CLOCK 6. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL startup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver D RXCMD internal reset update power ...
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... During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce power consumption. During power-up, if CHIP_SELECT_N is LOW, the PLL is powered and the ISP1504 operates normally. If CHIP_SELECT_N is HIGH: ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) Hi-Z (input) Rev. 01 — 19 October 2006 ...
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... SELECT_N DATA[7:0] DIR NXT STP Fig 8. Entering and exiting 3-state in normal mode ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C exiting 3-state mode 3-stated pins input ignored Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver 004aaa690 © NXP B.V. 2006. All rights reserved ...
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... Power source used 0 internal and external V 0 internal V BUS 1 external fault detector circuits that output a digital fault BUS Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver exiting 3-state mode exiting suspend mode 004aaa691 . BUS power sources are disabled BUS ...
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... RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive packets when NXT is LOW. An example is shown in refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Table 10. Any values other than those in Command Command description ...
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... LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1504 detects a change DM, an RXCMD will be sent to the link with the new LINESTATE[1:0] value. The value given on LINESTATE[1:0] depends on the setting of various registers. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C voltage state: For an explanation of the V voltage SESS_END < V ...
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... BUS state provides several options and must be BUS voltage indicators, as shown in Figure BUS state encoding”. BUS Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Chirp squelch !squelch and HS_Differential_Receiver_Output !squelch and !HS_Differential_Receiver_Output invalid state are directly taken from ...
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... external circuit must be used to BUS sufficient level for operation. SESS_VLD must be enabled to detect the Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver (0, X) RXCMD (1, 0) A_VBUS_VLD complement output (1, 1) ...
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... LOW level, allowing the B-device to safely initiate V When the ISP1504 has detected a SYNC pattern on the USB bus, it signals an HostDisconnect is encoded into the RxEvent field of the RXCMD. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver BUS Section 9.8.1. © ...
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... D extended immediate register write register read Table 13 the peripheral is in low-power mode, it must wake 0 Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver TXCMD (EXTW extended register read 004aaa710 Figure 13 © NXP B.V. 2006. All rights reserved. does not ...
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... After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 . ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... MODE J (01b) SE0 (00b) LINE STATE DP DM Timing is not to scale. Fig 13. USB reset and high-speed detection handshake (chirp) sequence ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C high-speed detection handshake (chirp) peripheral chirp TXCMD K 00 NOPID 00 (HS) 01 (chirp) squelch peripheral chirp K (10b) (00b) ...
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... Table 16 for correct USB system operation. Examples of high-speed Figure 15 Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Figure 14. For details on USB ISP1504 ISP1504 ISP1504 asserts DIR, ISP1504 deasserts causing ...
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... DIR STP NXT TX end delay (two to five clocks) Fig 15. High-speed transmit-to-transmit packet timing ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Low-speed Definition link delay 77 to 247 Number of clocks a host link must wait before driving the TXCMD for the second packet. In high-speed, the link starts counting from the assertion of STP for the fi ...
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... PRE PID, after which the pull-up resistor can hold the J state on the bus. An example transmit packet is shown in In preamble mode, the ISP1504 can also receive low-speed packets from the full-speed bus. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C USB interpacket delay (8 to 192 high-speed bit times) IDLE link decision time ( clocks) Figure 17. ...
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... After the EOP is completed, the host link sets OPMODE[1:0] to 00b for normal operation. The peripheral link sees the EOP and also resumes normal operation. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C TXCMD (low-speed packet ID) FS IDLE (min LS SYNC ...
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... Product data sheet SUSPEND RESUME K TXCMD TXCMD (REGW) NOPID LINESTATE J LINE STATE K 00b 10b K Figure 19 Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver EOP IDLE K TXCMD ... 10b 00b SE0 J SE0 J 00b SE0 J timing is not to scale, and does not © ...
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... OPMODE to 00b for normal high-speed operation. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C terminations enabled (TERMSELECT is set to 0b). The peripheral has its terminations (TERMSELECT is set to 0b). The peripheral link sees terminations (TERMSELECT is set to 0b). The host link sets Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver terminations, and enables the 1 ...
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... OP 00b MODE SUSPEND M !SQUELCH SQUELCH (01b) (00b) LINE STATE DP DM Timing is not to scale. Fig 19. High-speed suspend and resume ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C FS SUSPEND RESUME K TXCMD TXCMD K K ... (REGW) NOPID 01b 10b FS J (01b (10b) LINESTATE J LINESTATE K 01b 10b ...
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... SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... TXCMD (NOPID) type. The ISP1504 does not provide a mechanism to control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C TXCMD TXCMD REGW NOPID ...
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... Pull-up and pull-down resistors on DP and DM • ID detector indicates if mini-A or mini-B plug is inserted • Charge and discharge resistors on V The following subsections describe how to use the ISP1504 OTG components. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C 00h 00h 00h 80h PID SYNC PID ...
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... The ISP1504 supports both 6-pin serial mode and 3-pin serial mode, controlled by bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 , Section 3.10. Figure 22 and respectively. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Section Section 9.4 this data sheet, V A_SESS_VLD . Comparators are described in Section Section 10.1.5 ...
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... DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0 Fig 23. Example of transmit followed by receive in 3-pin serial mode ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C TRANSMIT DATA EOP SYNC TRANSMIT DATA EOP SYNC Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver RECEIVE DATA ...
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... LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 18 shows the bit description of the register. Table 18. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access VENDOR_ID_ R LOW[7:0] ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Size Address (6 bits) (bits [1] [2] [ 00h - - 8 ...
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... Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h 22 RESET OPMODE[1: R/W/S/C R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver 19. Table 20. 21 TERM XCVRSELECT[1:0] SELECT 0 0 R/W/S/C R/W/S/C © NXP B.V. 2006. All rights reserved. ...
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... Interface Control register (address R = 07h to 09h 07h 08h 09h) bit allocation Bit 7 6 Symbol INTF_ IND_PASS PROT_DIS THRU Reset 0 0 Access R/W/S/C R/W/S/C ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Table 24 provides the bit allocation of the register IND_ reserved CLOCK_ COMPL SUSPENDM R/W/S/C R/W/S/C R/W/S/C Rev. 01 — ...
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... Control register is given in Table 26. OTG Control register (address R = 0Ah to 0Ch 0Ah 0Bh 0Ch) bit allocation Bit 7 6 Symbol USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset 0 0 Access R/W/S/C R/W/S/C ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Section 9.5.2.2. Section 9.5.2.2. Table 26 DRV_ CHRG_ DISCHRG_ VBUS VBUS VBUS ...
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... BUS Table 28 shows the bit allocation of the register ID_GND_R SESS_ END_R 0 1 R/W/S/C R/W/S/C R/W/S/C Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver overcurrent indicator. BUS supply. Using an BUS . If DRV_VBUS_EXT is set to logic 1, BUS pulsing SRP. The link must BUS SESS_ ...
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... ID_GND_F SESS_ END_F 0 1 R/W/S/C R/W/S/C R/W/S/C Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on Table 32) indicates the current value of the interrupt source signal. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver SESS_ VBUS_ VALID_F VALID_F DISCON_F ...
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... Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD. BUS Cleared when this register is read. 0 HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on HOST_DISCON. Cleared when this register is read. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C ID_GND SESS_ END X 0 ...
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... Power Control register (address R = 3Dh to 3Fh 3Dh 3Eh 3Fh) bit allocation Bit 7 6 Symbol reserved Reset 0 0 Access R/W/S/C R/W/S/C ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C reserved Description reserved Line State 1: Contains the current value of LINESTATE 1. Line State 0: Contains the current value of LINESTATE 0. ...
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... Addresses 40h to FFh are not implemented. Operating on these addresses will have no effect on the PHY. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... Specification Rev. 2.0 . For details on the requirements for C HIGH VOLTAGE DC SOURCE Fig 24. Human body ESD test model 11.2 ESD test conditions A detailed report on test setup and results is available on request. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C to GND to achieve this 4 kV ESD protection (see BUS 1500 charge current ...
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... CC(I/O) V input voltage I T ambient temperature amb [1] V should be less than or equal to V CC(I/O) ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Conditions on pins CLOCK, STP, DATA[7:0], RESET_N and CHIP_SELECT_N on pins V , FAULT and PSW_N BUS on pin XTAL1 on pin ID pins DP, DM, ID, V and GND; BUS I < ...
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... LI Output levels V LOW-level output voltage OL V HIGH-level output voltage I OH ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions charge pump disabled low-power mode; V valid detector BUS disabled ...
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... CC CC(I/O) Symbol Parameter Output levels V HIGH-level output voltage OH V LOW-level output voltage OL I HIGH-level output current OH I LOW-level output current OL ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C = +85 C; unless otherwise specified. amb Conditions Min = V 0.4 V 4.8 O CC(I/ 0 < V < CC(I/O) 45 interface protect enabled ...
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... CHIRPJ V Chirp K level (differential voltage) CHIRPK Leakage current I off-state leakage current LZ Capacitance C input capacitance in ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions includes V range DI pull-up on pin DP; ...
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... BUS cp(C_A)-(C_B O(VBUS) comparators BUS = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions for A-device and B-device Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Min Typ Max 14.25 15 15.75 14.25 15 15.75 [1] 40.5 45 49.5 [1] 40 ...
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... C; unless otherwise specified. amb Conditions ID_PULLUP is logic +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Min Typ Max 281 680 - 656 1100 - ...
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... BUS 004aaa878 108 I CC(cp) (mA) 106 104 102 100 40 3.5 3.6 V (V) CC(cp) I CC(cp) Fig 28. Charge pump supply current vs. temperature Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver 004aaa877 = 3 3 (mA) O(VBUS) output voltage vs. V output current BUS 004aaa879 ...
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... PLL startup time startup(PLL) t output CLOCK start-up time startup(o)(CLOCK) [1] RMS = Root Mean Square. ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions 4 capacitor each on pins REG1V8 and REG3V3 ...
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... CLOCK t NXT output delay with respect to d(NXT) the rising edge of pin CLOCK ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C = +85 C; unless otherwise specified. amb = +25 C; unless otherwise specified. Conditions 20 pF total external load per pin ...
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... LF t rise and fall time matching t LRFM ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C …continued = +85 C; unless otherwise specified. amb = +25 C; unless otherwise specified. Conditions 20 pF total external load per pin 20 pF total external load ...
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... Single-ended receiver t single-ended propagation PLH(se) delay (LOW to HIGH) t single-ended propagation PHL(se) delay (HIGH to LOW) ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C …continued = +85 C; unless otherwise specified. amb = 3 +25 C; unless otherwise specified. amb Conditions TX_DAT, TX_SE0 to DP, DM; see Figure 30 TX_DAT, TX_SE0 to DP, DM ...
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... OH 0.3 V logic output + 0 004aaa574 Fig 32. Timing of DP and DM to RX_RCV, RX_DP and RX_DM t t su(STP) h(STP su(DATA) h(DATA) Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver 0 PLH(drv) PHL(drv) V CRS V V CRS CRS t t PLH(rcv) PHL(rcv) ...
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... XTAL1 pin that has a DC offset For detailed information and alternative interface options, refer to the Interfacing to the ISP1504/5/6 (AN10048) application note. [1] ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Value Comment 0 mA), 270 nF (50 mA 470 nF (50 mA) 4 ...
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... RECEPTACLE SHIELD 6 SHIELD SHIELD IP4059CX5/LF 8 SHIELD 9 D ESD C VBUS (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 34. Using the ISP1504 with an OTG Controller; internal charge pump is utilized and crystal is attached V V CC(I/ bypass DATA0 C bypass C bypass 1 V CC(I/ RREF RREF ...
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V IN FAULT CHARGE R pullup PUMP OUT V BUS USB MINI-AB GND 5 RECEPTACLE SHIELD 6 SHIELD ...
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... SHIELD C1 6 SHIELD IP4059CX5/LF 7 SHIELD 8 D ESD C VBUS (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 36. Using the ISP1504 with a standard USB Host Controller; external 5 V source with built-in FAULT and external square wave input on XTAL1 V V CC(I/ bypass DATA0 1 32 ...
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... GND 4 STANDARD-B SHIELD RECEPTACLE SHIELD 6 IP4059CX5/LF SHIELD 7 SHIELD ESD (1) Frequency is version dependent: ISP1504ABS: 19.2 MHz; ISP1504CBS: 26 MHz. Fig 37. Using the ISP1504 with a standard USB Peripheral Controller; external crystal V CC(I/ bypass C bypass DATA0 C bypass 1 V CC(I/ RREF RREF 3 DM ...
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... max. 0.05 0.30 5 0.2 0.00 0.18 4.9 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION IEC SOT617 Fig 38. Package outline SOT617-1 (HVQFN32) ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C 1 1/2 24 ...
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... Solder bath specifications, including temperature and impurities ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 39. Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Figure 39) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Non-Return-to-Zero Inverted On-The-Go [1] Physical Layer Packet Identifier Power-On Reset Receive Command Single-Ended Zero Start-Of-Frame Session Request Protocol Synchronous Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver peak temperature time 001aac844 © NXP B.V. 2006. All rights reserved ...
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... USB Implementers Forum UTMI+ Low Pin Interface USB 2.0 Transceiver Macrocell Interface USB 2.0 Transceiver Macrocell Interface Plus Data sheet status Product data sheet Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver Change notice Supersedes - - © NXP B.V. 2006. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver © NXP B.V. 2006. All rights reserved ...
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... Table 28. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .51 ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Table 29. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh 0Dh 0Eh 0Fh) bit description . . . . . . . . . . . . . . . . . . . . . 52 Table 30. USB Interrupt Enable Falling Edge register (address R = 10h to 12h 10h 11h 12h) bit allocation ...
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... NXP Semiconductors Table 58. Lead-free process (from J-STD-020C .76 Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . .78 ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C Rev. 01 — 19 October 2006 ULPI HS USB OTG transceiver continued >> © NXP B.V. 2006. All rights reserved ...
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... Controller; external crystal . . . . . . . . . . . . . . . . . 73 Fig 38. Package outline SOT617-1 (HVQFN32 Fig 39. Temperature profiles for large and small components output BUS output current . . . .63 valid BUS Rev. 01 — 19 October 2006 ISP1504A; ISP1504C ULPI HS USB OTG transceiver continued >> © NXP B.V. 2006. All rights reserved ...
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... DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.9.16 STP 7.9.17 NXT 7.9.18 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9.19 CHIP_SELECT_N 7.9.20 GND (die pad Modes of operation . . . . . . . . . . . . . . . . . . . . . 15 ISP1504A_ISP1504C_1 Product data sheet ISP1504A; ISP1504C 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 Synchronous mode . . . . . . . . . . . . . . . . . . . . 15 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 16 8.1.3 6-pin full-speed or low-speed serial mode . . . 17 8.1.4 3-pin full-speed or low-speed serial mode . . . 17 8.2 USB and OTG state transitions . . . . . . . . . . . 18 9 Protocol description . . . . . . . . . . . . . . . . . . . . 20 9 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 October 2006 Document identifier: ISP1504A_ISP1504C_1 All rights reserved. ...