KSZ8893-MQL Micrel Semiconductor, Inc., KSZ8893-MQL Datasheet

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KSZ8893-MQL

Manufacturer Part Number
KSZ8893-MQL
Description
Integrated 3-Port 10/100 Managed Switch with PHYs
Manufacturer
Micrel Semiconductor, Inc.
Datasheet
General Description
The KSZ8893MQL, a highly integrated layer 2
managed switch, is designed for low port count,
cost-sensitive 10/100 Mbps switch systems. It offers
an extensive feature set that includes rate limiting,
tag/port-based VLAN, QoS priority, management,
management information base (MIB) counters,
RMII/MII/SNI, and CPU control/data interfaces to
effectively address both current and emerging Fast
Ethernet applications.
The KSZ8893MQL contains two 10/100 transceivers
___________________________________________________________________________________________________
Functional Diagram
November 2005
P1 LED[3:0]
P2 LED[3:0]
HP AUTO
HP AUTO
RMII/MII/
MDIX
MDIX
MIIM
SMI
SNI
I2C
SPI
T/TX/FX
10/100
10/100
PHY 1
PHY 2
DRIVERS
T/TX
LED
1
REGISTERS
CONTROL
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
Integrated 3-Port 10/100 Managed Switch with PHYs
SNI
SPI
with patented mixed-signal low-power technology,
three media access control (MAC) units, a high-
speed non-blocking switch fabric, a dedicated
address lookup engine, and an on-chip frame buffer
memory.
Both PHY units support 10BASE-T and 100BASE-
TX. In addition, one PHY unit supports 100BASE-
FX.
The KSZ8893MQL comes in a lead-free package,
and is also available in industrial temperature-grade.
(see Ordering Information).
KSZ8893MQL/MQLI
Data Sheet Rev. 1.1
CONFIGURATION
STRAP IN
MANAGEMENT
MANAGEMENT
1K LOOK-UP
INTERFACE
COUNTERS
BUFFERS
EEPROM
BUFFER
ENGINE
QUEUE
FRAME
MIB
M9999-111705

Related parts for KSZ8893-MQL

KSZ8893-MQL Summary of contents

Page 1

... General Description The KSZ8893MQL, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, tag/port-based VLAN, QoS priority, management, management information base (MIB) counters, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications ...

Page 2

... Applications requiring port redundancy and port monitoring – Sensor devices in redundant ring topology Note: 1. Reduces cost and time of PCB re-spin. LinkMD is a trademark of Micrel, Inc. Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. 2 KSZ8893MQL/MQLI +85 C M9999-111705 ...

Page 3

... Seoul 135-080 Korea Taipei, 11468 Taiwan, R.O.C. Singapore 199555 Yokohama, Kanagawa 220-8543 Japan Newbury, Berks RG14 5QS UK Courtaboeuf Cedex 91944 France Masterton New Zealand 3 KSZ8893MQL/MQLI Telephone Fax +1 (408) 944-0800 +1 (408) 474-1000 +1 (609) 654-0078 +1 (609) 546-0989 +1 (972) 393-2533 +1 (972) 393-2540 +1 (408) 944-0800 +1 (408) 914-7878 ...

Page 4

... Micrel Revision History Revision Date 1.0 6/30/05 1.1 11/17/05 November 2005 Summary of Changes Initial release Updated ordering information Updated package information Updated default register values Updated current consumption description Changed device reference in datasheet from KS8893M to KSZ8893MQL Added repeater mode description 4 KSZ8893MQL/MQLI M9999-111705 ...

Page 5

... Half-Duplex Backpressure .............................................................................................................................................31 Broadcast Storm Protection ...........................................................................................................................................32 MII Interface Operation........................................................................................................................................................32 RMII Interface Operation .....................................................................................................................................................33 SNI (7-Wire) Operation ........................................................................................................................................................34 MII Management (MIIM) Interface .......................................................................................................................................35 Serial Management Interface (SMI) ....................................................................................................................................36 Repeater Mode.....................................................................................................................................................................36 Advanced Switch Functions ................................................................................................................37 Spanning Tree Support.......................................................................................................................................................37 Special Tagging Mode.........................................................................................................................................................38 IGMP Support ......................................................................................................................................................................39 IGMP Snooping .............................................................................................................................................................39 November 2005 5 KSZ8893MQL/MQLI M9999-111705 ...

Page 6

... Register 12 (0x0C): Global Control 10...........................................................................................................................60 Register 13 (0x0D): Global Control 11...........................................................................................................................61 Register 14 (0x0E): Global Control 12 ...........................................................................................................................61 Register 15 (0x0F): Global Control 13 ...........................................................................................................................61 Port Registers......................................................................................................................................................................62 Register 16 (0x10): Port 1 Control 0 ..............................................................................................................................62 Register 32 (0x20): Port 2 Control 0 ..............................................................................................................................62 Register 48 (0x30): Port 3 Control 0 ..............................................................................................................................62 November 2005 6 KSZ8893MQL/MQLI M9999-111705 ...

Page 7

... Register 105 (0x69): TOS Priority Control Register 9 ....................................................................................................79 Register 106 (0x6A): TOS Priority Control Register 10..................................................................................................79 Register 107 (0x6B): TOS Priority Control Register 11..................................................................................................80 Register 108 (0x6C): TOS Priority Control Register 12 .................................................................................................80 Register 109 (0x6D): TOS Priority Control Register 13 .................................................................................................81 November 2005 7 KSZ8893MQL/MQLI M9999-111705 ...

Page 8

... MAC Mode MII Timing ...................................................................................................................................................96 PHY Mode MII Timing....................................................................................................................................................97 RMII Timing ..........................................................................................................................................................................98 SPI Timing............................................................................................................................................................................99 Input Timing ...................................................................................................................................................................99 Output Timing ..............................................................................................................................................................100 Auto-Negotiation Timing...................................................................................................................................................101 Reset Timing .......................................................................................................................................102 Reset Circuit........................................................................................................................................103 Selection of Isolation Transformers..................................................................................................104 Selection of Reference Crystal ..........................................................................................................104 Package Information...........................................................................................................................105 November 2005 (1) ..............................................................................................................92 ..................................................................................................................93 8 KSZ8893MQL/MQLI M9999-111705 ...

Page 9

... Figure 4. Destination Address Lookup Flow Chart, Stage 1 .............................................................................................................29 Figure 5. Destination Address Resolution Flow Chart, Stage 2 .......................................................................................................30 Figure 6. 802.1p Priority Field Format .................................................................................................................................................41 Figure 7. KSZ8893MQL EEPROM Configuration Timing Diagram....................................................................................................43 Figure 8. SPI Write Data Cycle..............................................................................................................................................................45 Figure 9. SPI Read Data Cycle ..............................................................................................................................................................46 Figure 10. SPI Multiple Write.................................................................................................................................................................46 Figure 11 ...

Page 10

... Table 12. STPID Egress Rules (Switch Port 3 to Processor).............................................................................................................39 Table 13. FID+DA Lookup in VLAN Mode ............................................................................................................................................40 Table 14. FID+SA Lookup in VLAN Mode ............................................................................................................................................41 Table 15. KSZ8893MQL SPI Connections............................................................................................................................................45 Table 16. Format of Static MAC Table (8 Entries)...............................................................................................................................86 Table 17. Format of Static VLAN Table (16 Entries) ...........................................................................................................................87 Table 18. Format of Dynamic MAC Address Table (1K Entries) .......................................................................................................88 Table 19. Format of “ ...

Page 11

... RPT_COL : Low (collision) RPT_LINK#/ port) : Low (link), High (no link), Toggles (receive activity) Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P1LED3 is pin 25. During reset, P1LED[2:0] are inputs for internal testing. 11 KSZ8893MQL/MQLI [LEDSEL1, LEDSEL0] [0, 0] [0, 1] — — Link/Act 100Link/Act Full duplex/Col ...

Page 12

... JK error) Notes: LEDSEL0 is external strap-in pin 70. LEDSEL1 is external strap-in pin 23. P2LED3 is pin 20. During reset, P2LED[2:0] are inputs for internal testing. Gnd Digital ground P 3.3V digital KSZ8893MQL/MQLI [LEDSEL1, LEDSEL0] [0, 0] [0, 1] — — Link/Act 100Link/Act Full duplex/Col 10Link/Act Speed Full duplex ...

Page 13

... Port 2 LED indicator Note: Internal pull-down is weak; it will not turn ON the LED. See description in pin 4. Gnd Digital ground P 1.2V digital VDD Provides V to KSZ8893MQL’s input power pins: V OUT_1V2 (pin 63), V (pins 91 and 123), and V DDC 57). Ipd LED display mode select See description in pins 1 and 4. ...

Page 14

... Ipd No connect Ipd No connect Ipu Chip power down input (active low) Gnd Analog ground P 1.2V analog V DD Gnd Analog ground I Factory test pin - float for normal operation I Factory test pin - float for normal operation 14 KSZ8893MQL/MQLI M9999-111705 ...

Page 15

... connect. Note: Clock is +/- 50ppm for both crystal and oscillator. Ipu Hardware reset pin (active low) I Unused pin – externally pull down for normal operation I Unused pin – externally pull down for normal operation 15 KSZ8893MQL/MQLI M9999-111705 ...

Page 16

... Strap option: Switch MII (default) = 100Mbps mode PU = 10Mbps mode I/O Switch MII receive data bit 0 Strap option: switch will accept packet size 1536 bytes (inclusive 1522 bytes (tagged), 1518 bytes (untagged) I/O Switch MII collision detect I/O Switch MII carrier sense 16 KSZ8893MQL/MQLI M9999-111705 ...

Page 17

... Note: an external pull-up is needed on this pin when use. I SPI slave mode: chip select (active low) When SPIS_N is high, the KSZ8893MQL is deselected and SPIQ is held in high impedance state. A high-to-low transition is used to initiate SPI data transfer. See description in pins 100 and 101. ...

Page 18

... SCL SDA SPIS_N [PS1, PS0] = [1, 1] – SMI-mode In this mode, the KSZ8893MQL provides access to all its internal 8-bit registers through its MDC and MDIO pins. Note: When (PS1, PS0) ≠ (1,1), the KSZ8893MQL provides access to its 16-bit MIIM registers through its MDC and MDIO pins. ...

Page 19

... Unused pin – externally pull down for normal operation I Unused pin – externally pull down for normal operation Ipd Scan Test Enable For normal operation, pull-down this pin to ground. Ipd Scan Test Scan Mux Enable For normal operation, pull-down this pin to ground. 19 KSZ8893MQL/MQLI M9999-111705 ...

Page 20

... UNUSED 119 UNUSED 120 UNUSED 121 UNUSED 122 DGND VDDC 123 UNUSED 124 UNUSED 125 UNUSED 126 TESTEN 127 SCANEN 128 November 2005 128-Pin PQFP (Top View) 20 KSZ8893MQL/MQLI 64 AGND 63 VDDAP 62 AGND 61 ISET 60 TEST2 59 TEST1 58 AGND 57 VDDA 56 TXP2 55 TXM2 54 AGND 53 RXP2 ...

Page 21

... The KSZ8893MQL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8893MQL has the flexibility to reside in either a managed or unmanaged design managed design, the host processor has complete control of the KSZ8893MQL via the SMI interface, MIIM interface, SPI bus bus ...

Page 22

... A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8893MQL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KSZ8893MQL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames. ...

Page 23

... The receiver clock is maintained active during idle periods in between data reception. Power Management The KSZ8893MQL features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register, or MIIM PHY register. In addition, there is a full chip power down mode. When activated, the entire chip is powered down. ...

Page 24

... Media Dependent Interface Transmit Pair Receive Pair Modular Connector (RJ-45) NIC November 2005 1 2 Straight 3 Cable Figure 1. Typical Straight Cable Connection 24 KSZ8893MQL/MQLI 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) M9999-111705 ...

Page 25

... KSZ8893MQL link partner is forced to bypass auto-negotiation, the KSZ8893MQL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8893MQL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The link up process is shown in the following flow diagram. ...

Page 26

... Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode Figure 3. Auto-Negotiation and Parallel Operation November 2005 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set 26 KSZ8893MQL/MQLI Listen for 10BASE-T Link Pulses No M9999-111705 ...

Page 27

... The ‘11’ case, invalid test, occurs when the KSZ8893MQL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8893MQL to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0] ...

Page 28

... Forwarding The KSZ8893MQL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...

Page 29

... Search VLAN table NO VLAN ID - Ingress VLAN filtering Valid? - Discard NPVID check YES FOUND Search Static This search is based on Table DA or DA+FID NOT FOUND FOUND This search is based on Dynamic Table DA+FID Search NOT FOUND Search complete. Get PTF1 from VLAN Table PTF1 29 KSZ8893MQL/MQLI M9999-111705 ...

Page 30

... These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KSZ8893MQL intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as " ...

Page 31

... The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8893MQL will flow control a port that has just received a packet if the destination port resource is busy. The KSZ8893MQL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802 ...

Page 32

... Note: These bits are not set as defaults, as this is not the IEEE standard. Broadcast Storm Protection The KSZ8893MQL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893MQL has the option to include “ ...

Page 33

... For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission. The KSZ8893MQL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device ...

Page 34

... Micrel The KSZ8893MQL filters error frames, and thus does not implement the RX_ER output signal. To detect error frames from RMII PHY devices, the SMTXER input signal of the KSZ8893MQL is connected to the RXER output signal of the RMII PHY device. Collision detection is implemented in accordance with the RMII Specification. ...

Page 35

... The KSZ8893MQL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8893MQL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification. ...

Page 36

... Repeater Mode The KSZ8893MQL supports repeater mode in 100BASE-TX Half Duplex mode. In repeater mode, all ingress packets are broadcast to the other two ports. MAC address checking and learning are disabled. Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured to 100BASE-TX Half Duplex mode ...

Page 37

... BPDU packets). The “overriding” bit is set so that the switch forwards those specific packets to the processor. The processor can send packets to the port(s) in this state. See “Special Tagging Mode” for details. Address learning is enabled on the port in this state. Table 9: Spanning Tree States 37 KSZ8893MQL/MQLI M9999-111705 ...

Page 38

... MAC table lookup to determine the forwarding port(s). The KSZ8893MQL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port setting, regardless of port states (disable, blocking, listening, learning). The table below shows the processor to switch egress rules when dealing with STPID ...

Page 39

... IPv6 next header = ( with hop-by-hop next header = 1 or 58) If the MLD option bit is set to “1”, the KSZ8893MQL traps packets with the following additional condition: • IPv6 next header = 43, 44, 50 with hop-by-hop next header = 43, 44, 50, 51, or ...

Page 40

... A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893MQL forwards the packet to both port 2 and port 3. The KSZ8893MQL can optionally even forward “bad” received packets to the “sniffer port”. ...

Page 41

... Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KSZ8893MQL. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2 and 3, respectively. QoS Priority Support The KSZ8893MQL provides Quality of Service (QoS) for applications such as VoIP and video conferencing ...

Page 42

... MAC address table is used to assign a dedicated MAC address to a specific port unicast MAC address is not recorded in the static table also not learned in the dynamic MAC table. The KSZ8893MQL is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14 ...

Page 43

... C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as defined in the KSZ8893MQL register map) with the exception of the “Read Only” status registers. After the de-assertion of reset, the KSZ8893MQL sequentially reads in the configuration data for all 121 registers, starting from register 0 ...

Page 44

... C slave mode by setting the KSZ8893MQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to “01”. 2. Power up the board and assert reset to the KSZ8893MQL. After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’. 3. Configure the desired register settings in the KSZ8893MQL, using the I 4. Read back and verify the register settings in the KSZ8893MQL, using the I 5. Write a ‘ ...

Page 45

... Enable SPI slave mode by setting the KSZ8893MQL strap-in pins PS[1:0] (pins 100 and 101, respectively) to “10”. 3. Power up the board and assert reset to the KSZ8893MQL. After reset, the “Start Switch” bit (register 1 bit [0]) is set to ‘0’. 4. Configure the desired register settings in the KSZ8893MQL, using the SPI write or multiple write command. ...

Page 46

... READ ADDRESS Byte 3 Figure 11. SPI Multiple Read 46 KSZ8893MQL/MQLI READ DATA Byte Byte ...

Page 47

... Micrel Loopback Support The KSZ8893MQL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end (Remote) Loopback. Far-end Loopback Far-end loopback is conducted between the KSZ8893MQL’s two PHY ports. The loopback path starts at the “ ...

Page 48

... Micrel Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8893MQL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx). ...

Page 49

... PHY2 Basic Control Register PHY2 Basic Status Register PHY2 Physical Identifier I PHY2 Physical Identifier II PHY2 Auto-Negotiation Advertisement Register PHY2 Auto-Negotiation Link Partner Ability Register PHY2 Not supported PHY2 LinkMD Control/Status PHY2 Not supported PHY2 Special Control/Status 49 KSZ8893MQL/MQLI 2 C, and SMI M9999-111705 ...

Page 50

... Normal operation (transmit on TXP / TXM pins) =1, Disable auto MDI-X =0, Enable auto MDI-X =1, Disable far-end fault detection =0, Normal operation =1, Disable transmit =0, Normal operation =1, Disable LED =0, Normal operation 50 KSZ8893MQL/MQLI Default Reference 0 0 Reg. 29, bit 0 Reg. 45, bit 0 0 Reg. 28, bit 6 Reg. 44, bit 6 1 Reg. 28, bit 7 Reg ...

Page 51

... No far-end fault detected =1, Auto-negotiation capable =0, Not auto-negotiation capable =1, Link is up =0, Link is down NOT SUPPORTED =0, Not extended register capable Description High order PHYID bits Description Low order PHYID bits 51 KSZ8893MQL/MQLI Default Reference 0 1 Always 1 1 Always 1 1 Always 1 1 Always 1 0000 ...

Page 52

... Do not advertise 10 half duplex ability 802.3 Description NOT SUPPORTED NOT SUPPORTED NOT SUPPORTED Link partner pause capability Link partner 100 full capability Link partner 100 half capability Link partner 10 full capability Link partner 10 half capability 52 KSZ8893MQL/MQLI Default Reference Reg. 28, bit 4 Reg. 44, bit Reg ...

Page 53

... Loopback: PMD/PMA of port 1’s PHY End: TXP1/TXM1 (port 1) Port 2 (reg. 42, bit 1 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port Normal Operation Reserved Do not change the default value. 53 KSZ8893MQL/MQLI Default Reference 0 Reg. 26, bit 4 Reg. 42, bit 4 00 Reg 26, bit[6:5] Reg 42, bit[6:5] 0 Reg ...

Page 54

... Switch Engine’s MAC Address Registers User Defined Registers Indirect Access Control Registers Indirect Data Registers Digital Testing Status Register Digital Testing Control Register Analog Testing Control Registers Analog Testing Status Register Analog Testing Control Register QM Debug Registers Description Chip family 54 KSZ8893MQL/MQLI Default 0x88 M9999-111705 ...

Page 55

... After an age cycle is complete, the age logic will return to normal aging (about 200 sec). Note: If any port is unplugged, all addresses will be automatically aged out. 55 KSZ8893MQL/MQLI Default 0x2 - - Default 0 ...

Page 56

... Note: Port mirroring is not supported if this bit is set to “0” “Broadcast Storm Protection” does not include multicast packets. Only DA = FF-FF-FF-FF-FF-FF packets will be regulated “Broadcast Storm Protection” includes DA = FF-FF-FF-FF-FF-FF and DA[40 packets carrier sense based backpressure is selected = 0, collision based backpressure is selected 56 KSZ8893MQL/MQLI Default ...

Page 57

... VLAN is disabled. =1, IGMP snoop is enabled. All IGMP packets will be forwarded to the Switch MII port. =0, IGMP snoop is disabled. IPv6 MLD snooping 1 = enable 0 = disable IPv6 MLD snooping option 1 = enable 0 = disable 57 KSZ8893MQL/MQLI Default SMRXD0 (pin 85) value during reset 1 Default 0 ...

Page 58

... PHY ports need to have auto-negotiation disabled enable MII interface half-duplex mode enable MII interface full-duplex mode enable full duplex flow control on Switch MII interface disable full duplex flow control on Switch MII interface. 58 KSZ8893MQL/MQLI Default Default 0 Pin SMRXD2 strap option. ...

Page 59

... The default is 1%. Description Reserved Do not change the default values. Description Reserved Do not change the default values. Description Reserved Do not change the default values. 59 KSZ8893MQL/MQLI Default Pin SMRXD1 strap option. Pull-down(0): Enable 100Mbps Pull-up(1): Enable 10Mbps Note: SMRXD1 has internal pull- down ...

Page 60

... Tag_0x0 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x0. November 2005 LEDSEL1 is also external strap-in pin #23. LEDSEL0 is also external strap-in pin #70. 60 KSZ8893MQL/MQLI Default LEDSEL1 (pin 23) value during reset 00 0 ...

Page 61

... N/A Note: Port 2 PHY address = (Port 1 PHY address 2-0 Reserved RO Reserved Do not change the default values. November 2005 Bit 2 stands for port 3. Bit 1 stands for port 2. Bit 0 stands for port 1. 61 KSZ8893MQL/MQLI Default Default 0 0x0 111 Default 00001 000 M9999-111705 ...

Page 62

... There is no priority differentiation even though packets are classified into high or low priority. 62 KSZ8893MQL/MQLI Default ...

Page 63

... Define the port’s egress port VLAN membership. The port can only communicate within the membership. Bit 2 stands for port 3, bit 1 stands for port 2, bit 0 stands for port 1. An ‘1’ includes a port in the membership. An ‘0’ excludes a port from membership. 63 KSZ8893MQL/MQLI Default ...

Page 64

... KSZ8893MQL/MQLI Default Pin value during reset: For port 1, ...

Page 65

... Ingress and Egress rate limiting calculations IFG bytes are not counted. Count Preamble bytes = 1, each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations preamble bytes are not counted. 65 KSZ8893MQL/MQLI Default 0x00 Default 0x01 Default 0x0 00 ...

Page 66

... Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). 66 KSZ8893MQL/MQLI Default 0x0 0x0 M9999-111705 ...

Page 67

... Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). 67 KSZ8893MQL/MQLI Default 0x0 0x0 M9999-111705 ...

Page 68

... Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). When TX multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 68 KSZ8893MQL/MQLI Default 0x0 0x0 M9999-111705 ...

Page 69

... Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10BT, rate settings above 10Mbps are set to the default value 0000 (Not limited). When TX multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 69 KSZ8893MQL/MQLI Default 0x0 0x0 M9999-111705 ...

Page 70

... Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 2’s PHY End: TXP2/TXM2 (port Normal Operation Bit[8] of VCT fault count Distance to the fault. It’s approximately 0.4m*vct_fault_count[8:0] Description Bits[7:0] of VCT fault count Distance to the fault. It’s approximately 0.4m*Vct_fault_count[8:0] 70 KSZ8893MQL/MQLI Default Default 0x00 M9999-111705 ...

Page 71

... KSZ8893MQL/MQLI Default For port 1, P1ANEN pin value during reset. For port 2, P2ANEN pin ...

Page 72

... Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) Port 2 Loopback (reg. 45, bit 0 = ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 2’s PHY End: TXP1/TXM1 (port normal operation 72 KSZ8893MQL/MQLI Default Note: Only port 1 supports fiber. This bit is applicable to port 1 only ...

Page 73

... Micrel Auto MDI/MDI-X mode Reserved Do not change the default value polarity is reversed 0 = polarity is not reversed 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 1 = receive flow control feature is active 0 = receive flow control feature is inactive 73 KSZ8893MQL/MQLI Default Default ...

Page 74

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x04. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x00. 74 KSZ8893MQL/MQLI Default Note: Only port 1 supports fiber. ...

Page 75

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x24. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x20. 75 KSZ8893MQL/MQLI Default Default ...

Page 76

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x44. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x40. 76 KSZ8893MQL/MQLI Default Default ...

Page 77

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x64. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x60. 77 KSZ8893MQL/MQLI Default Default ...

Page 78

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x84. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x80. 78 KSZ8893MQL/MQLI Default Default ...

Page 79

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xA4. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xA0. 79 KSZ8893MQL/MQLI Default Default ...

Page 80

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xC4. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xC0. 80 KSZ8893MQL/MQLI Default Default ...

Page 81

... The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xE4. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xE0. 81 KSZ8893MQL/MQLI Default Default ...

Page 82

... IP TOS/DiffServ/Traffic Class value is 0xF4. The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0xF0. Description Description Description Description Description Description 82 KSZ8893MQL/MQLI Default Default 0x00 Default 0x10 Default 0xA1 ...

Page 83

... Micrel Registers 118 to 120 Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8893MQL and the external processor. Register 118 (0x76): User Defined Register 1 ...

Page 84

... Bits [47:40] of indirect data Description Bits [39:32] of indirect data Description Bits [31:24] of indirect data Description Bits [23:16] of indirect data Description Bits [15:8] of indirect data Description Bits [7:0] of indirect data Description Factory testing Factory testing 84 KSZ8893MQL/MQLI Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 Default 0000_0000 ...

Page 85

... Factory testing (dgt_actl3) Description Factory testing Description Factory testing (dgt_actl4) Description Factory testing QM_Debug bit[7:0] Description Reserved Do not change the default values. Factory testing QM_Debug bit[8] 85 KSZ8893MQL/MQLI Default 0x3F Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x00 Default 0x40 Default ...

Page 86

... Micrel Static MAC Address Table The KSZ8893MQL supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KSZ8893MQL searches both tables to make a packet forwarding decision. response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes ...

Page 87

... Write to reg. 122 (0x7A) with 0x07 VLAN Table The KSZ8893MQL uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID), VID (VLAN ID), and VLAN membership as described in the following table. ...

Page 88

... Write to reg. 130 (0x82), VLAN table bits [15:8] Write to reg. 131 (0x83), VLAN table bits [7:0] Write to reg. 121 (0x79) with 0x04 Write to reg. 122 (0x7A) with 0x06 Dynamic MAC Address Table The KSZ8893MQL maintains the dynamic MAC address table. Read access is allowed only. Bit Name 71 Data Not ...

Page 89

... Micrel MIB (Management Information Base) Counters The KSZ8893MQL provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” Bit ...

Page 90

... Successfully Tx frames on a port for which Tx is inhibited by more than one collision R/W Description N/A Reserved RO Counter Value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 90 KSZ8893MQL/MQLI Default N/A 0 M9999-111705 ...

Page 91

... If bit restart (reread) from this register counter bits [29:24] // Read MIB counter selected // Trigger the read operation // If bit there was a counter overflow valid bit [30 bit restart (reread) from this register counter bits [29:24] // Read MIB counter selected // Trigger the read operation 91 KSZ8893MQL/MQLI M9999-111705 ...

Page 92

... V DDATX DDARX DDIO All Inputs –0.5V to 4.0V All Outputs –0.5V to 4.0V N/A N/A -55°C to 150°C Symbol Min 1.14V DDA DDAP DDC 3.135V DDATX DDARX DDIO 0° θ KSZ8893MQL/MQLI Typ Max 1.26V 1.2V 3.465V 3.3V 70°C 125°C 32°C/W M9999-111705 ...

Page 93

... Parameter Supply Current - Current consumption is for the single 3.3V supply KSZ8893MQL device only, and includes the 1.2V supply voltages (VDDA, VDDAP, VDDC) that are provided by the KSZ8893MQL via power output pin 22. - Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V - for 10BASE-T ...

Page 94

... Figure 15. EEPROM Interface Output Timing Diagram Timing Parameter Description Clock cycle t cyc1 Setup time t s1 Hold time t h1 Output valid t ov1 November 2005 ts1 tcyc1 th1 tcyc1 tov1 Min Typ 16384 20 20 4096 4112 Table 23. EEPROM Timing Parameters 94 KSZ8893MQL/MQLI Max Unit 4128 ns M9999-111705 ...

Page 95

... Setup time t s2 Hold time t h2 Output valid t ov2 November 2005 ts2 tcyc2 th2 Figure 16. SNI Input Timing Diagram tcyc2 tov2 Figure 17. SNI Output Timing Diagram Min Typ 100 Table 24. SNI Timing Parameters 95 KSZ8893MQL/MQLI Max Unit M9999-111705 ...

Page 96

... Clock cycle 100BASE-TX (100BASE-TX) tcyc3 Clock cycle 10BASE-T (10BASE-T) ts3 Setup time th3 Hold time tov3 Output valid November 2005 t t cyc3 s 3 Min Table 25. MAC Mode MII Timing Parameters 96 KSZ8893MQL/MQLI Typ Max Unit 40 ns 400 M9999-111705 ...

Page 97

... Setup time th4 Hold time tov4 Output valid November 2005 t t cyc4 ov4 cyc4 Figure 21. PHY Mode MII Timing – Data Input to MII Min Table 26. PHY Mode MII Timing Parameters 97 KSZ8893MQL/MQLI t h4 Typ Max Unit 40 ns 400 M9999-111705 ...

Page 98

... Hold time tod Output delay November 2005 Figure 22: RMII Timing – Data Received from RMII tcyc t od Figure 23: RMII Timing – Data Input to RMII Min 4 2 2.8 Table 27: RMII Timing Parameters 98 KSZ8893MQL/MQLI Typ Max Unit M9999-111705 ...

Page 99

... SPIS_N inactive setup time SPIS_N deselect time Data input setup time Data input hold time Clock rise time Clock fall time Data input rise time Data input fall time Table 28. SPI Input Timing Parameters 99 KSZ8893MQL/MQLI tSHSL tSHCH tCHCL LSB Min Max Units 5 MHz ...

Page 100

... Description Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time Clock low time SPIQ rise time SPIQ fall time SPIQ disable time Table 29. SPI Output Timing Parameters 100 KSZ8893MQL/MQLI tCL tSHQZ LSB tQLQH tQHQL Min Max Units 5 MHz ...

Page 101

... lock D ata P ulse P ulse Figure 26: Auto-Negotiation Timing Min 8 55.5 111 17 Table 30: Auto-Negotiation Timing Parameters 101 KSZ8893MQL/MQLI urst C lock D ata P ulse P ulse Typ Max Units 100 ns 64 69.5 µs 128 139 µ ...

Page 102

... Micrel Reset Timing The KSZ8893MQL reset timing requirement is summarized in the following figure and table. Supply Voltage RST_N Strap-In Value Strap-In/ Output Pin Parameter Stable supply voltages to reset High t sr Configuration setup time Configuration hold time ch Reset to strap-in pin output t rc After the de-assertion of reset recommended to wait a minimum of 100 us before starting programming on the managed interface (I2C slave, SPI slave, SMI, MIIM) ...

Page 103

... Micrel Reset Circuit The reset circuit in Figure 28 is recommended for powering up the KSZ8893MQL if reset is triggered only by the power supply. KS8893M The reset circuit in Figure 29 is recommended for applications where reset is driven by another device (e.g., CPU, FPGA, etc),. At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8893MQL device ...

Page 104

... SI-50170 LF8505 LF-H41S H1102 H1260 HB726 LF-H41S Table 33. Qualified Single Port Magnetics Value 25.00000 ± Table 34. Typical Reference Crystal Characteristics 104 KSZ8893MQL/MQLI Test Condition 100mV, 100kHz, 8mA 1MHz (min.) 0MHz – 65MHz Auto MDI-X Number of Port Yes 1 Yes 1 Yes 1 Yes 1 ...

Page 105

... Micrel Package Information November 2005 Figure 30. 128-Pin PQFP Package 105 KSZ8893MQL/MQLI M9999-111705 ...

Page 106

... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. November 2005 FAX: +1 (408) 474 1000 WEB: http:/www.micrel.com © 2005 Micrel, Incorporated. 106 KSZ8893MQL/MQLI M9999-111705 ...

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