LPC1342FBD48,151 NXP Semiconductors, LPC1342FBD48,151 Datasheet

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LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller flash and 8 kB SRAM; USB device Rev. 3 — 10 August 2010 1. General description The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of ...

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... NXP Semiconductors Other peripherals General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Four general purpose counter/timers with a total of four capture inputs and 13 match outputs. Programmable WatchDog Timer (WDT). System tick timer. Serial Wire Debug and Serial Wire Trace port. High-current output driver (20 mA) on one pin. ...

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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name LPC1311FHN33 HVQFN33 LPC1313FBD48 LQFP48 LPC1313FHN33 HVQFN33 LPC1342FHN33 HVQFN33 LPC1343FBD48 LQFP48 LPC1343FHN33 HVQFN33 4.1 Ordering options Table 2. Ordering options for LPC1311/13/42/43 Type number Flash LPC1311FHN33 8 kB LPC1313FBD48 32 kB LPC1313FHN33 32 kB LPC1342FHN33 ...

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... NXP Semiconductors 5. Block diagram HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (2) DTR, DSR , CTS, (2) (2) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 (1) LPC1342/43 only. (2) LQFP48 package only. Fig 1. Block diagram ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 2. LPC1343 LQFP48 package LPC1311_13_42_43 Product data sheet 1 PIO2_6 XTALIN 6 LPC1343FBD48 7 XTALOUT PIO2_7 11 12 PIO2_8 All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...

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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 3. LPC1342/43 HVQFN33 package LPC1311_13_42_43 Product data sheet terminal 1 index area PIO2_0/DTR 1 2 RESET/PIO0_0 3 XTALIN 4 LPC1342FHN33 XTALOUT 5 LPC1343FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...

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... NXP Semiconductors PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 4. LPC1313 LQFP48 package LPC1311_13_42_43 Product data sheet LPC1313FBD48 All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller 36 PIO3_0 35 R/PIO1_2/AD3/CT32B1_MAT1 34 R/PIO1_1/AD2/CT32B1_MAT0 ...

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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_2/SSEL/CT16B0_CAP0 Fig 5. LPC1311_13_42_43 Product data sheet terminal 1 index area 1 PIO2_0/DTR RESET/PIO0_0 2 3 XTALIN 4 LPC1311FHN33 LPC1313FHN33 5 XTALOUT PIO1_8/CT16B1_CAP0 7 8 Transparent top view LPC1311/13 HVQFN33 package All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...

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... NXP Semiconductors 6.2 Pin description Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [2] RESET/PIO0_0 3 yes [3] PIO0_1/CLKOUT/ 4 yes CT32B0_MAT2/ USB_FTOGGLE [3] PIO0_2/SSEL/ 10 yes CT16B0_CAP0 [3] PIO0_3/USB_VBUS 14 yes [4] PIO0_4/SCL 15 yes [4] PIO0_5/SDA 16 yes [3] PIO0_6/ 22 yes USB_CONNECT/ SCK [3] PIO0_7/CTS 23 yes [3] PIO0_8/MISO/ 27 yes CT16B0_MAT0 [3] PIO0_9/MOSI/ ...

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... NXP Semiconductors Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [3] SWCLK/PIO0_10/ 29 yes SCK/CT16B0_MAT2 [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1/ 34 yes AD2/CT32B1_MAT0 [5] R/PIO1_2/ 35 yes AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/ 39 yes AD4/ CT32B1_MAT2 [5] PIO1_4/AD5/ 40 yes CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS/ 45 yes CT32B0_CAP0 [3] PIO1_6/RXD/ 46 yes ...

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... NXP Semiconductors Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [3] PIO1_7/TXD/ 47 yes CT32B0_MAT1 [3] PIO1_8/CT16B1_C 9 yes AP0 [3] PIO1_9/CT16B1_M 17 yes AT0 [5] PIO1_10/AD6/ 30 yes CT16B1_MAT1 [5] PIO1_11/AD7 42 yes [3] PIO2_0/DTR 2 yes [3] PIO2_1/DSR 13 yes [3] PIO2_2/DCD 26 yes [3] PIO2_3/RI 38 yes [3] PIO2_4 18 yes [3] PIO2_4 19 yes [3] PIO2_5 21 yes ...

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... NXP Semiconductors Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [7] XTALIN 6 - [7] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. ...

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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [4] PIO0_5/SDA 11 yes [3] PIO0_6/ 15 yes USB_CONNECT/ SCK [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO/ 17 yes CT16B0_MAT0 [3] PIO0_9/MOSI/ 18 yes CT16B0_MAT1/ SWO [3] SWCLK/PIO0_10/ 19 yes SCK/ CT16B0_MAT2 [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2/ 23 yes CT32B1_MAT0 ...

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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [5] R/PIO1_2/AD3/ 24 yes CT32B1_MAT1 [5] SWDIO/PIO1_3/ 25 yes AD4/ CT32B1_MAT2 [5] PIO1_4/AD5/ 26 yes CT32B1_MAT3/WA KEUP [3] PIO1_5/RTS/ 30 yes CT32B0_CAP0 [3] PIO1_6/RXD/ 31 yes CT32B0_MAT0 [3] PIO1_7/TXD/ 32 yes CT32B0_MAT1 [3] PIO1_8/ 7 yes CT16B1_CAP0 [3] PIO1_9/ 12 yes CT16B1_MAT0 [5] PIO1_10/AD6/ 20 yes ...

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... NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [7] XTALIN 4 - [7] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. ...

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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices ...

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... NXP Semiconductors LPC1311/13/42/ private peripheral bus AHB peripherals APB peripherals 1 GB AHB SRAM bit-band alias addressing 0 boot ROM 8 kB SRAM (LPC1313/1343) I-code/D-code memory space 4 kB SRAM (LPC1311/1342 on-chip flash (LPC1313/43 on-chip flash (LPC1342 on-chip flash (LPC1311 Fig 6. LPC1311/13/42/43 memory map 7.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M3 ...

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... NXP Semiconductors • 8 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...

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... NXP Semiconductors 7.9 USB interface (LPC1342/43 only) The Universal Serial Bus (USB 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller ...

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... NXP Semiconductors The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.10.1 Features • Maximum UART data bit rate of 4.5 MBit/s. • 16-byte receive and transmit FIFOs. • Register locations conform to 16C550 industry standard. ...

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... NXP Semiconductors 7.12.1 Features • The I pins. The I • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • ...

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... NXP Semiconductors • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • four external outputs corresponding to match registers, with the following capabilities: – ...

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... NXP Semiconductors Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 7 IRC oscillator watchdog oscillator IRC oscillator SYSTEM PLL ...

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... NXP Semiconductors 7.17.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. ...

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... NXP Semiconductors 7.17.5 Power control The LPC1311/13/42/43 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...

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... NXP Semiconductors 7.18.2 Reset Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset, power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller ...

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... NXP Semiconductors 7.18.5 Boot loader The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. ...

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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...

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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins and RESET pin; see I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...

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... NXP Semiconductors Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7); see I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input ...

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... NXP Semiconductors Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage V HIGH-level output OH voltage C transceiver capacitance pin to GND ...

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... NXP Semiconductors Table 8. ADC static characteristics = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz amb Symbol Parameter E absolute error T R voltage source interface vsi resistance R input resistance i [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (E ...

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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 8. ADC characteristics LPC1311_13_42_43 Product data sheet ...

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... NXP Semiconductors 9.1 BOD static characteristics Table °C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual): • ...

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... NXP Semiconductors (mA) Fig 9. (mA) Fig 10. Typical supply current versus temperature in Active mode LPC1311_13_42_43 Product data sheet MHz MHz 36 MHz 9 24 MHz 6 12 MHz 3 2.0 2 °C; active mode entered executing code Conditions: T amb internal pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; ...

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... NXP Semiconductors (mA) Fig 11. Typical supply current versus temperature in Sleep mode (μA) Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks LPC1311_13_42_43 Product data sheet 10 72 MHz MHz 6 36 MHz 4 24 MHz 12 MHz 2 0 −40 −15 Conditions 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; system DD oscillator and system PLL enabled ...

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... NXP Semiconductors (μA) Fig 13. Typical supply current versus temperature in Deep power-down mode 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...

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... NXP Semiconductors Table 10. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA n/a 12 MHz GPIO - 0.21 IOCONFIG - 0.00 I2C - 0.03 ROM - 0.04 SSP - 0.11 UART - 0.20 WDT - 0.01 USB - - USB - 1.84 9.4 Electrical pin characteristics V Fig 14. High-drive output: Typical HIGH-level output voltage V ...

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... NXP Semiconductors (mA) Fig 15. I (mA) Fig 16. Typical LOW-level output current I LPC1311_13_42_43 Product data sheet 0.2 Conditions 3 pins PIO0_4 and PIO0_5 C-bus pins (high current sink): Typical LOW-level output current I LOW-level output voltage 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors V Fig 17. Typical HIGH-level output voltage V (μA) Fig 18. Typical pull-up current I LPC1311_13_42_43 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. ...

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... NXP Semiconductors (μA) Fig 19. Typical pull-down current I LPC1311_13_42_43 Product data sheet ° °C −40 ° Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller versus input voltage V i 002aae989 ...

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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 11. Flash characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter N endurance endu t retention time ret t erase time er t programming time prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. ...

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... NXP Semiconductors 10.3 Internal oscillators Table 13. Dynamic characteristics: IRC = −40 °C to +85 °C; 2.7 V ≤ amb Symbol Parameter f internal RC oscillator frequency osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...

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... NXP Semiconductors 10.4 I/O pins Table 15. Dynamic characteristics: I/O pins = −40 °C to +85 °C; 3.0 V ≤ amb Symbol Parameter t rise time r t fall time f [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 16. Dynamic characteristic −40 °C to +85 °C. ...

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... NXP Semiconductors could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t [8] The maximum t HD;DAT transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. ...

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... NXP Semiconductors 10.6 SSP interface Table 17. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time h(Q) SSP slave T PCLK cycle time ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 ...

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... NXP Semiconductors 10.7 USB interface (LPC1342/43 only) Table 18. Dynamic characteristics: USB pins (full-speed pF 1.5 kΩ Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...

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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions (LPC1342/43 only) LPC134x Fig 26. LPC1342/43 USB interface on a self-powered device LPC134x Fig 27. LPC1342/43 USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a ...

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... NXP Semiconductors Fig 28. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...

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... NXP Semiconductors Table 19. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 20. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...

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... NXP Semiconductors 11.4 Standard I/O pad configuration Figure 30 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output pin configured as digital input pin configured as analog input Fig 30 ...

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... NXP Semiconductors 11.5 Reset pad configuration Fig 31. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1311/13/42/43 chip. • ...

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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...

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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors 13. Abbreviations Table 21. Acronym A/D ADC AHB AMBA APB BOD EOP ETM FIFO GPIO HID I/O LSB MSC PHY PLL SE0 SPI SSI SSP SoF TCM TTL UART USB LPC1311_13_42_43 Product data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus ...

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... NXP Semiconductors 14. Revision history Table 22. Revision history Document ID Release date LPC1311_13_42_43 v.3 20100810 Modifications: LPC1311_13_42_43 v.2 20100506 LPC1311_13_42_43 v.1 20091211 LPC1311_13_42_43 Product data sheet Data sheet status Product data sheet • limit changed to −6500 V (min) /+6500 V (max ESD • Reset state of pins and start logic functionality added in • ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... For sales office addresses, please send an email to: LPC1311_13_42_43 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 16 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 16 7.3 On-chip flash program memory . . . . . . . . . . . 16 7 ...

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... NXP Semiconductors 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...